Struct esp32h2::spi0::spi_mem_cache_sctrl::R
source · pub struct R(_);
Expand description
Register SPI_MEM_CACHE_SCTRL
reader
Implementations§
source§impl R
impl R
sourcepub fn spi_mem_cache_usr_saddr_4byte(&self) -> SPI_MEM_CACHE_USR_SADDR_4BYTE_R
pub fn spi_mem_cache_usr_saddr_4byte(&self) -> SPI_MEM_CACHE_USR_SADDR_4BYTE_R
Bit 0 - For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: enable, 0:disable.
sourcepub fn spi_mem_usr_sram_dio(&self) -> SPI_MEM_USR_SRAM_DIO_R
pub fn spi_mem_usr_sram_dio(&self) -> SPI_MEM_USR_SRAM_DIO_R
Bit 1 - For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable
sourcepub fn spi_mem_usr_sram_qio(&self) -> SPI_MEM_USR_SRAM_QIO_R
pub fn spi_mem_usr_sram_qio(&self) -> SPI_MEM_USR_SRAM_QIO_R
Bit 2 - For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable
sourcepub fn spi_mem_usr_wr_sram_dummy(&self) -> SPI_MEM_USR_WR_SRAM_DUMMY_R
pub fn spi_mem_usr_wr_sram_dummy(&self) -> SPI_MEM_USR_WR_SRAM_DUMMY_R
Bit 3 - For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write operations.
sourcepub fn spi_mem_usr_rd_sram_dummy(&self) -> SPI_MEM_USR_RD_SRAM_DUMMY_R
pub fn spi_mem_usr_rd_sram_dummy(&self) -> SPI_MEM_USR_RD_SRAM_DUMMY_R
Bit 4 - For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read operations.
sourcepub fn spi_mem_cache_sram_usr_rcmd(&self) -> SPI_MEM_CACHE_SRAM_USR_RCMD_R
pub fn spi_mem_cache_sram_usr_rcmd(&self) -> SPI_MEM_CACHE_SRAM_USR_RCMD_R
Bit 5 - For SPI0, In the external RAM mode cache read external RAM for user define command.
sourcepub fn spi_mem_sram_rdummy_cyclelen(&self) -> SPI_MEM_SRAM_RDUMMY_CYCLELEN_R
pub fn spi_mem_sram_rdummy_cyclelen(&self) -> SPI_MEM_SRAM_RDUMMY_CYCLELEN_R
Bits 6:11 - For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. The register value shall be (bit_num-1).
sourcepub fn spi_mem_sram_addr_bitlen(&self) -> SPI_MEM_SRAM_ADDR_BITLEN_R
pub fn spi_mem_sram_addr_bitlen(&self) -> SPI_MEM_SRAM_ADDR_BITLEN_R
Bits 14:19 - For SPI0, In the external RAM mode, it is the length in bits of address phase. The register value shall be (bit_num-1).
sourcepub fn spi_mem_cache_sram_usr_wcmd(&self) -> SPI_MEM_CACHE_SRAM_USR_WCMD_R
pub fn spi_mem_cache_sram_usr_wcmd(&self) -> SPI_MEM_CACHE_SRAM_USR_WCMD_R
Bit 20 - For SPI0, In the external RAM mode cache write sram for user define command
sourcepub fn spi_mem_sram_oct(&self) -> SPI_MEM_SRAM_OCT_R
pub fn spi_mem_sram_oct(&self) -> SPI_MEM_SRAM_OCT_R
Bit 21 - reserved
sourcepub fn spi_mem_sram_wdummy_cyclelen(&self) -> SPI_MEM_SRAM_WDUMMY_CYCLELEN_R
pub fn spi_mem_sram_wdummy_cyclelen(&self) -> SPI_MEM_SRAM_WDUMMY_CYCLELEN_R
Bits 22:27 - For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. The register value shall be (bit_num-1).