esp32c61-0.2.0
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docs.rs

Rust

esp32c61 0.2.0

Peripheral access crate for the ESP32-C61

Crate
Source
Builds
Feature flags

..
bus0_acs_conflict_cnt.rs
bus0_acs_hit_cnt.rs
bus0_acs_miss_cnt.rs
bus1_acs_conflict_cnt.rs
bus1_acs_hit_cnt.rs
bus1_acs_miss_cnt.rs
bypass_cache_conf.rs
cache_acs_cnt_ctrl.rs
cache_acs_cnt_int_clr.rs
cache_acs_cnt_int_ena.rs
cache_acs_cnt_int_raw.rs
cache_acs_cnt_int_st.rs
cache_acs_fail_ctrl.rs
cache_acs_fail_int_clr.rs
cache_acs_fail_int_ena.rs
cache_acs_fail_int_raw.rs
cache_acs_fail_int_st.rs
cache_addr.rs
cache_atomic_conf.rs
cache_autoload_buf_clr_ctrl.rs
cache_autoload_ctrl.rs
cache_autoload_sct0_addr.rs
cache_autoload_sct0_size.rs
cache_autoload_sct1_addr.rs
cache_autoload_sct1_size.rs
cache_autoload_sct2_addr.rs
cache_autoload_sct2_size.rs
cache_autoload_sct3_addr.rs
cache_autoload_sct3_size.rs
cache_blocksize_conf.rs
cache_cachesize_conf.rs
cache_clock_gate.rs
cache_ctrl.rs
cache_data_mem_acs_conf.rs
cache_debug_bus.rs
cache_freeze_ctrl.rs
cache_l2_bypass_cache_conf.rs
cache_l2_cache_access_attr_ctrl.rs
cache_l2_cache_acs_cnt_ctrl.rs
cache_l2_cache_acs_cnt_int_clr.rs
cache_l2_cache_acs_cnt_int_ena.rs
cache_l2_cache_acs_cnt_int_raw.rs
cache_l2_cache_acs_cnt_int_st.rs
cache_l2_cache_acs_fail_addr.rs
cache_l2_cache_acs_fail_ctrl.rs
cache_l2_cache_acs_fail_id_attr.rs
cache_l2_cache_acs_fail_int_clr.rs
cache_l2_cache_acs_fail_int_ena.rs
cache_l2_cache_acs_fail_int_raw.rs
cache_l2_cache_acs_fail_int_st.rs
cache_l2_cache_addr.rs
cache_l2_cache_autoload_buf_clr_ctrl.rs
cache_l2_cache_autoload_ctrl.rs
cache_l2_cache_autoload_sct0_addr.rs
cache_l2_cache_autoload_sct0_size.rs
cache_l2_cache_autoload_sct1_addr.rs
cache_l2_cache_autoload_sct1_size.rs
cache_l2_cache_autoload_sct2_addr.rs
cache_l2_cache_autoload_sct2_size.rs
cache_l2_cache_autoload_sct3_addr.rs
cache_l2_cache_autoload_sct3_size.rs
cache_l2_cache_blocksize_conf.rs
cache_l2_cache_cachesize_conf.rs
cache_l2_cache_ctrl.rs
cache_l2_cache_data_mem_acs_conf.rs
cache_l2_cache_debug_bus.rs
cache_l2_cache_freeze_ctrl.rs
cache_l2_cache_miss_access_ctrl.rs
cache_l2_cache_object_ctrl.rs
cache_l2_cache_preload_addr.rs
cache_l2_cache_preload_ctrl.rs
cache_l2_cache_preload_rst_ctrl.rs
cache_l2_cache_preload_size.rs
cache_l2_cache_prelock_conf.rs
cache_l2_cache_prelock_sct0_addr.rs
cache_l2_cache_prelock_sct1_addr.rs
cache_l2_cache_prelock_sct_size.rs
cache_l2_cache_sync_preload_exception.rs
cache_l2_cache_sync_preload_int_clr.rs
cache_l2_cache_sync_preload_int_ena.rs
cache_l2_cache_sync_preload_int_raw.rs
cache_l2_cache_sync_preload_int_st.rs
cache_l2_cache_sync_rst_ctrl.rs
cache_l2_cache_tag_mem_acs_conf.rs
cache_l2_cache_way_object.rs
cache_l2_cache_wrap_around_ctrl.rs
cache_l2_dbus0_acs_conflict_cnt.rs
cache_l2_dbus0_acs_hit_cnt.rs
cache_l2_dbus0_acs_miss_cnt.rs
cache_l2_dbus0_acs_nxtlvl_rd_cnt.rs
cache_l2_dbus0_acs_nxtlvl_wr_cnt.rs
cache_l2_dbus1_acs_conflict_cnt.rs
cache_l2_dbus1_acs_hit_cnt.rs
cache_l2_dbus1_acs_miss_cnt.rs
cache_l2_dbus1_acs_nxtlvl_rd_cnt.rs
cache_l2_dbus1_acs_nxtlvl_wr_cnt.rs
cache_l2_dbus2_acs_conflict_cnt.rs
cache_l2_dbus2_acs_hit_cnt.rs
cache_l2_dbus2_acs_miss_cnt.rs
cache_l2_dbus2_acs_nxtlvl_rd_cnt.rs
cache_l2_dbus2_acs_nxtlvl_wr_cnt.rs
cache_l2_dbus3_acs_conflict_cnt.rs
cache_l2_dbus3_acs_hit_cnt.rs
cache_l2_dbus3_acs_miss_cnt.rs
cache_l2_dbus3_acs_nxtlvl_rd_cnt.rs
cache_l2_dbus3_acs_nxtlvl_wr_cnt.rs
cache_l2_ibus0_acs_conflict_cnt.rs
cache_l2_ibus0_acs_hit_cnt.rs
cache_l2_ibus0_acs_miss_cnt.rs
cache_l2_ibus0_acs_nxtlvl_rd_cnt.rs
cache_l2_ibus1_acs_conflict_cnt.rs
cache_l2_ibus1_acs_hit_cnt.rs
cache_l2_ibus1_acs_miss_cnt.rs
cache_l2_ibus1_acs_nxtlvl_rd_cnt.rs
cache_l2_ibus2_acs_conflict_cnt.rs
cache_l2_ibus2_acs_hit_cnt.rs
cache_l2_ibus2_acs_miss_cnt.rs
cache_l2_ibus2_acs_nxtlvl_rd_cnt.rs
cache_l2_ibus3_acs_conflict_cnt.rs
cache_l2_ibus3_acs_hit_cnt.rs
cache_l2_ibus3_acs_miss_cnt.rs
cache_l2_ibus3_acs_nxtlvl_rd_cnt.rs
cache_l2_unallocate_buffer_clear.rs
cache_level_split0.rs
cache_level_split1.rs
cache_lock_addr.rs
cache_lock_ctrl.rs
cache_lock_map.rs
cache_lock_size.rs
cache_miss_access_ctrl.rs
cache_object_ctrl.rs
cache_preload_ctrl.rs
cache_preload_rst_ctrl.rs
cache_prelock_conf.rs
cache_prelock_sct0_addr.rs
cache_redundancy_sig0.rs
cache_redundancy_sig1.rs
cache_redundancy_sig2.rs
cache_redundancy_sig3.rs
cache_redundancy_sig4.rs
cache_sync_addr.rs
cache_sync_ctrl.rs
cache_sync_map.rs
cache_sync_preload_exception.rs
cache_sync_preload_int_clr.rs
cache_sync_preload_int_ena.rs
cache_sync_preload_int_raw.rs
cache_sync_preload_int_st.rs
cache_sync_rst_ctrl.rs
cache_sync_size.rs
cache_tag_mem_acs_conf.rs
cache_trace_ena.rs
cache_way_object.rs
cache_wrap_around_ctrl.rs
dbus0_acs_nxtlvl_rd_cnt.rs
dbus0_acs_nxtlvl_wr_cnt.rs
dbus1_acs_nxtlvl_rd_cnt.rs
dbus1_acs_nxtlvl_wr_cnt.rs
dbus2_acs_conflict_cnt.rs
dbus2_acs_hit_cnt.rs
dbus2_acs_miss_cnt.rs
dbus2_acs_nxtlvl_rd_cnt.rs
dbus2_acs_nxtlvl_wr_cnt.rs
dbus3_acs_conflict_cnt.rs
dbus3_acs_hit_cnt.rs
dbus3_acs_miss_cnt.rs
dbus3_acs_nxtlvl_rd_cnt.rs
dbus3_acs_nxtlvl_wr_cnt.rs
dcache_acs_fail_addr.rs
dcache_acs_fail_id_attr.rs
dcache_preload_addr.rs
dcache_preload_size.rs
dcache_prelock_sct1_addr.rs
dcache_prelock_sct_size.rs
ibus0_acs_conflict_cnt.rs
ibus0_acs_hit_cnt.rs
ibus0_acs_miss_cnt.rs
ibus0_acs_nxtlvl_rd_cnt.rs
ibus1_acs_conflict_cnt.rs
ibus1_acs_hit_cnt.rs
ibus1_acs_miss_cnt.rs
ibus1_acs_nxtlvl_rd_cnt.rs
ibus2_acs_conflict_cnt.rs
ibus2_acs_hit_cnt.rs
ibus2_acs_miss_cnt.rs
ibus2_acs_nxtlvl_rd_cnt.rs
ibus3_acs_conflict_cnt.rs
ibus3_acs_hit_cnt.rs
ibus3_acs_miss_cnt.rs
ibus3_acs_nxtlvl_rd_cnt.rs
icache0_acs_fail_addr.rs
icache0_acs_fail_id_attr.rs
icache0_autoload_ctrl.rs
icache0_autoload_sct0_addr.rs
icache0_autoload_sct0_size.rs
icache0_autoload_sct1_addr.rs
icache0_autoload_sct1_size.rs
icache0_preload_addr.rs
icache0_preload_ctrl.rs
icache0_preload_size.rs
icache0_prelock_conf.rs
icache0_prelock_sct0_addr.rs
icache0_prelock_sct1_addr.rs
icache0_prelock_sct_size.rs
icache1_acs_fail_addr.rs
icache1_acs_fail_id_attr.rs
icache1_autoload_ctrl.rs
icache1_autoload_sct0_addr.rs
icache1_autoload_sct0_size.rs
icache1_autoload_sct1_addr.rs
icache1_autoload_sct1_size.rs
icache1_preload_addr.rs
icache1_preload_ctrl.rs
icache1_preload_size.rs
icache1_prelock_conf.rs
icache1_prelock_sct0_addr.rs
icache1_prelock_sct1_addr.rs
icache1_prelock_sct_size.rs
icache2_acs_fail_addr.rs
icache2_acs_fail_id_attr.rs
icache2_autoload_ctrl.rs
icache2_autoload_sct0_addr.rs
icache2_autoload_sct0_size.rs
icache2_autoload_sct1_addr.rs
icache2_autoload_sct1_size.rs
icache2_preload_addr.rs
icache2_preload_ctrl.rs
icache2_preload_size.rs
icache2_prelock_conf.rs
icache2_prelock_sct0_addr.rs
icache2_prelock_sct1_addr.rs
icache2_prelock_sct_size.rs
icache3_acs_fail_addr.rs
icache3_acs_fail_id_attr.rs
icache3_autoload_ctrl.rs
icache3_autoload_sct0_addr.rs
icache3_autoload_sct0_size.rs
icache3_autoload_sct1_addr.rs
icache3_autoload_sct1_size.rs
icache3_preload_addr.rs
icache3_preload_ctrl.rs
icache3_preload_size.rs
icache3_prelock_conf.rs
icache3_prelock_sct0_addr.rs
icache3_prelock_sct1_addr.rs
icache3_prelock_sct_size.rs
icache_blocksize_conf.rs
icache_cachesize_conf.rs
icache_ctrl.rs
unallocate_buffer_clear.rs