Type Alias W

pub type W = W<CFG_DATA7_SPEC>;

Register CFG_DATA7 writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn pin_state(&mut self) -> PIN_STATE_W<'_, CFG_DATA7_SPEC>

Bits 0:7 - configure cis addr 318 and 574

pub fn chip_state(&mut self) -> CHIP_STATE_W<'_, CFG_DATA7_SPEC>

Bits 8:15 - configure cis addr 312, 315, 568 and 571

pub fn sdio_rst(&mut self) -> SDIO_RST_W<'_, CFG_DATA7_SPEC>

Bit 16 - soft reset control for sdio module

pub fn sdio_ioready0(&mut self) -> SDIO_IOREADY0_W<'_, CFG_DATA7_SPEC>

Bit 17 - sdio io ready, high enable

pub fn sdio_mem_pd(&mut self) -> SDIO_MEM_PD_W<'_, CFG_DATA7_SPEC>

Bit 18 - sdio memory power down, high active

pub fn esdio_data1_int_en(&mut self) -> ESDIO_DATA1_INT_EN_W<'_, CFG_DATA7_SPEC>

Bit 19 - enable sdio interrupt on data1 line

pub fn sdio_switch_volt_sw( &mut self, ) -> SDIO_SWITCH_VOLT_SW_W<'_, CFG_DATA7_SPEC>

Bit 20 - control switch voltage change to 1.8V by software. 0:3.3V,1:1.8V

pub fn ddr50_blk_len_fix_en( &mut self, ) -> DDR50_BLK_LEN_FIX_EN_W<'_, CFG_DATA7_SPEC>

Bit 21 - enable block length to be fixed to 512 bytes in ddr50 mode

pub fn clk_en(&mut self) -> CLK_EN_W<'_, CFG_DATA7_SPEC>

Bit 22 - sdio apb clock for configuration force on control:0-gating,1-force on.

pub fn sddr50(&mut self) -> SDDR50_W<'_, CFG_DATA7_SPEC>

Bit 23 - configure if support sdr50 mode in cccr

pub fn ssdr104(&mut self) -> SSDR104_W<'_, CFG_DATA7_SPEC>

Bit 24 - configure if support sdr104 mode in cccr

pub fn ssdr50(&mut self) -> SSDR50_W<'_, CFG_DATA7_SPEC>

Bit 25 - configure if support ddr50 mode in cccr

pub fn sdtd(&mut self) -> SDTD_W<'_, CFG_DATA7_SPEC>

Bit 26 - configure if support driver type D in cccr

pub fn sdta(&mut self) -> SDTA_W<'_, CFG_DATA7_SPEC>

Bit 27 - configure if support driver type A in cccr

pub fn sdtc(&mut self) -> SDTC_W<'_, CFG_DATA7_SPEC>

Bit 28 - configure if support driver type C in cccr

pub fn sai(&mut self) -> SAI_W<'_, CFG_DATA7_SPEC>

Bit 29 - configure if support asynchronous interrupt in cccr

pub fn sdio_wakeup_clr(&mut self) -> SDIO_WAKEUP_CLR_W<'_, CFG_DATA7_SPEC>

Bit 30 - clear sdio_wake_up signal after the chip wakes up