esp32c6/lp_uart/
int_ena.rs1#[doc = "Register `INT_ENA` reader"]
2pub type R = crate::R<INT_ENA_SPEC>;
3#[doc = "Register `INT_ENA` writer"]
4pub type W = crate::W<INT_ENA_SPEC>;
5#[doc = "Field `RXFIFO_FULL` reader - This is the enable bit for rxfifo_full_int_st register."]
6pub type RXFIFO_FULL_R = crate::BitReader;
7#[doc = "Field `RXFIFO_FULL` writer - This is the enable bit for rxfifo_full_int_st register."]
8pub type RXFIFO_FULL_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `TXFIFO_EMPTY` reader - This is the enable bit for txfifo_empty_int_st register."]
10pub type TXFIFO_EMPTY_R = crate::BitReader;
11#[doc = "Field `TXFIFO_EMPTY` writer - This is the enable bit for txfifo_empty_int_st register."]
12pub type TXFIFO_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `PARITY_ERR` reader - This is the enable bit for parity_err_int_st register."]
14pub type PARITY_ERR_R = crate::BitReader;
15#[doc = "Field `PARITY_ERR` writer - This is the enable bit for parity_err_int_st register."]
16pub type PARITY_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `FRM_ERR` reader - This is the enable bit for frm_err_int_st register."]
18pub type FRM_ERR_R = crate::BitReader;
19#[doc = "Field `FRM_ERR` writer - This is the enable bit for frm_err_int_st register."]
20pub type FRM_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `RXFIFO_OVF` reader - This is the enable bit for rxfifo_ovf_int_st register."]
22pub type RXFIFO_OVF_R = crate::BitReader;
23#[doc = "Field `RXFIFO_OVF` writer - This is the enable bit for rxfifo_ovf_int_st register."]
24pub type RXFIFO_OVF_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `DSR_CHG` reader - This is the enable bit for dsr_chg_int_st register."]
26pub type DSR_CHG_R = crate::BitReader;
27#[doc = "Field `DSR_CHG` writer - This is the enable bit for dsr_chg_int_st register."]
28pub type DSR_CHG_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `CTS_CHG` reader - This is the enable bit for cts_chg_int_st register."]
30pub type CTS_CHG_R = crate::BitReader;
31#[doc = "Field `CTS_CHG` writer - This is the enable bit for cts_chg_int_st register."]
32pub type CTS_CHG_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `BRK_DET` reader - This is the enable bit for brk_det_int_st register."]
34pub type BRK_DET_R = crate::BitReader;
35#[doc = "Field `BRK_DET` writer - This is the enable bit for brk_det_int_st register."]
36pub type BRK_DET_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `RXFIFO_TOUT` reader - This is the enable bit for rxfifo_tout_int_st register."]
38pub type RXFIFO_TOUT_R = crate::BitReader;
39#[doc = "Field `RXFIFO_TOUT` writer - This is the enable bit for rxfifo_tout_int_st register."]
40pub type RXFIFO_TOUT_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `SW_XON` reader - This is the enable bit for sw_xon_int_st register."]
42pub type SW_XON_R = crate::BitReader;
43#[doc = "Field `SW_XON` writer - This is the enable bit for sw_xon_int_st register."]
44pub type SW_XON_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `SW_XOFF` reader - This is the enable bit for sw_xoff_int_st register."]
46pub type SW_XOFF_R = crate::BitReader;
47#[doc = "Field `SW_XOFF` writer - This is the enable bit for sw_xoff_int_st register."]
48pub type SW_XOFF_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `GLITCH_DET` reader - This is the enable bit for glitch_det_int_st register."]
50pub type GLITCH_DET_R = crate::BitReader;
51#[doc = "Field `GLITCH_DET` writer - This is the enable bit for glitch_det_int_st register."]
52pub type GLITCH_DET_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `TX_BRK_DONE` reader - This is the enable bit for tx_brk_done_int_st register."]
54pub type TX_BRK_DONE_R = crate::BitReader;
55#[doc = "Field `TX_BRK_DONE` writer - This is the enable bit for tx_brk_done_int_st register."]
56pub type TX_BRK_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `TX_BRK_IDLE_DONE` reader - This is the enable bit for tx_brk_idle_done_int_st register."]
58pub type TX_BRK_IDLE_DONE_R = crate::BitReader;
59#[doc = "Field `TX_BRK_IDLE_DONE` writer - This is the enable bit for tx_brk_idle_done_int_st register."]
60pub type TX_BRK_IDLE_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `TX_DONE` reader - This is the enable bit for tx_done_int_st register."]
62pub type TX_DONE_R = crate::BitReader;
63#[doc = "Field `TX_DONE` writer - This is the enable bit for tx_done_int_st register."]
64pub type TX_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `AT_CMD_CHAR_DET` reader - This is the enable bit for at_cmd_char_det_int_st register."]
66pub type AT_CMD_CHAR_DET_R = crate::BitReader;
67#[doc = "Field `AT_CMD_CHAR_DET` writer - This is the enable bit for at_cmd_char_det_int_st register."]
68pub type AT_CMD_CHAR_DET_W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `WAKEUP` reader - This is the enable bit for uart_wakeup_int_st register."]
70pub type WAKEUP_R = crate::BitReader;
71#[doc = "Field `WAKEUP` writer - This is the enable bit for uart_wakeup_int_st register."]
72pub type WAKEUP_W<'a, REG> = crate::BitWriter<'a, REG>;
73impl R {
74 #[doc = "Bit 0 - This is the enable bit for rxfifo_full_int_st register."]
75 #[inline(always)]
76 pub fn rxfifo_full(&self) -> RXFIFO_FULL_R {
77 RXFIFO_FULL_R::new((self.bits & 1) != 0)
78 }
79 #[doc = "Bit 1 - This is the enable bit for txfifo_empty_int_st register."]
80 #[inline(always)]
81 pub fn txfifo_empty(&self) -> TXFIFO_EMPTY_R {
82 TXFIFO_EMPTY_R::new(((self.bits >> 1) & 1) != 0)
83 }
84 #[doc = "Bit 2 - This is the enable bit for parity_err_int_st register."]
85 #[inline(always)]
86 pub fn parity_err(&self) -> PARITY_ERR_R {
87 PARITY_ERR_R::new(((self.bits >> 2) & 1) != 0)
88 }
89 #[doc = "Bit 3 - This is the enable bit for frm_err_int_st register."]
90 #[inline(always)]
91 pub fn frm_err(&self) -> FRM_ERR_R {
92 FRM_ERR_R::new(((self.bits >> 3) & 1) != 0)
93 }
94 #[doc = "Bit 4 - This is the enable bit for rxfifo_ovf_int_st register."]
95 #[inline(always)]
96 pub fn rxfifo_ovf(&self) -> RXFIFO_OVF_R {
97 RXFIFO_OVF_R::new(((self.bits >> 4) & 1) != 0)
98 }
99 #[doc = "Bit 5 - This is the enable bit for dsr_chg_int_st register."]
100 #[inline(always)]
101 pub fn dsr_chg(&self) -> DSR_CHG_R {
102 DSR_CHG_R::new(((self.bits >> 5) & 1) != 0)
103 }
104 #[doc = "Bit 6 - This is the enable bit for cts_chg_int_st register."]
105 #[inline(always)]
106 pub fn cts_chg(&self) -> CTS_CHG_R {
107 CTS_CHG_R::new(((self.bits >> 6) & 1) != 0)
108 }
109 #[doc = "Bit 7 - This is the enable bit for brk_det_int_st register."]
110 #[inline(always)]
111 pub fn brk_det(&self) -> BRK_DET_R {
112 BRK_DET_R::new(((self.bits >> 7) & 1) != 0)
113 }
114 #[doc = "Bit 8 - This is the enable bit for rxfifo_tout_int_st register."]
115 #[inline(always)]
116 pub fn rxfifo_tout(&self) -> RXFIFO_TOUT_R {
117 RXFIFO_TOUT_R::new(((self.bits >> 8) & 1) != 0)
118 }
119 #[doc = "Bit 9 - This is the enable bit for sw_xon_int_st register."]
120 #[inline(always)]
121 pub fn sw_xon(&self) -> SW_XON_R {
122 SW_XON_R::new(((self.bits >> 9) & 1) != 0)
123 }
124 #[doc = "Bit 10 - This is the enable bit for sw_xoff_int_st register."]
125 #[inline(always)]
126 pub fn sw_xoff(&self) -> SW_XOFF_R {
127 SW_XOFF_R::new(((self.bits >> 10) & 1) != 0)
128 }
129 #[doc = "Bit 11 - This is the enable bit for glitch_det_int_st register."]
130 #[inline(always)]
131 pub fn glitch_det(&self) -> GLITCH_DET_R {
132 GLITCH_DET_R::new(((self.bits >> 11) & 1) != 0)
133 }
134 #[doc = "Bit 12 - This is the enable bit for tx_brk_done_int_st register."]
135 #[inline(always)]
136 pub fn tx_brk_done(&self) -> TX_BRK_DONE_R {
137 TX_BRK_DONE_R::new(((self.bits >> 12) & 1) != 0)
138 }
139 #[doc = "Bit 13 - This is the enable bit for tx_brk_idle_done_int_st register."]
140 #[inline(always)]
141 pub fn tx_brk_idle_done(&self) -> TX_BRK_IDLE_DONE_R {
142 TX_BRK_IDLE_DONE_R::new(((self.bits >> 13) & 1) != 0)
143 }
144 #[doc = "Bit 14 - This is the enable bit for tx_done_int_st register."]
145 #[inline(always)]
146 pub fn tx_done(&self) -> TX_DONE_R {
147 TX_DONE_R::new(((self.bits >> 14) & 1) != 0)
148 }
149 #[doc = "Bit 18 - This is the enable bit for at_cmd_char_det_int_st register."]
150 #[inline(always)]
151 pub fn at_cmd_char_det(&self) -> AT_CMD_CHAR_DET_R {
152 AT_CMD_CHAR_DET_R::new(((self.bits >> 18) & 1) != 0)
153 }
154 #[doc = "Bit 19 - This is the enable bit for uart_wakeup_int_st register."]
155 #[inline(always)]
156 pub fn wakeup(&self) -> WAKEUP_R {
157 WAKEUP_R::new(((self.bits >> 19) & 1) != 0)
158 }
159}
160#[cfg(feature = "impl-register-debug")]
161impl core::fmt::Debug for R {
162 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
163 f.debug_struct("INT_ENA")
164 .field("rxfifo_full", &self.rxfifo_full())
165 .field("txfifo_empty", &self.txfifo_empty())
166 .field("parity_err", &self.parity_err())
167 .field("frm_err", &self.frm_err())
168 .field("rxfifo_ovf", &self.rxfifo_ovf())
169 .field("dsr_chg", &self.dsr_chg())
170 .field("cts_chg", &self.cts_chg())
171 .field("brk_det", &self.brk_det())
172 .field("rxfifo_tout", &self.rxfifo_tout())
173 .field("sw_xon", &self.sw_xon())
174 .field("sw_xoff", &self.sw_xoff())
175 .field("glitch_det", &self.glitch_det())
176 .field("tx_brk_done", &self.tx_brk_done())
177 .field("tx_brk_idle_done", &self.tx_brk_idle_done())
178 .field("tx_done", &self.tx_done())
179 .field("at_cmd_char_det", &self.at_cmd_char_det())
180 .field("wakeup", &self.wakeup())
181 .finish()
182 }
183}
184impl W {
185 #[doc = "Bit 0 - This is the enable bit for rxfifo_full_int_st register."]
186 #[inline(always)]
187 pub fn rxfifo_full(&mut self) -> RXFIFO_FULL_W<INT_ENA_SPEC> {
188 RXFIFO_FULL_W::new(self, 0)
189 }
190 #[doc = "Bit 1 - This is the enable bit for txfifo_empty_int_st register."]
191 #[inline(always)]
192 pub fn txfifo_empty(&mut self) -> TXFIFO_EMPTY_W<INT_ENA_SPEC> {
193 TXFIFO_EMPTY_W::new(self, 1)
194 }
195 #[doc = "Bit 2 - This is the enable bit for parity_err_int_st register."]
196 #[inline(always)]
197 pub fn parity_err(&mut self) -> PARITY_ERR_W<INT_ENA_SPEC> {
198 PARITY_ERR_W::new(self, 2)
199 }
200 #[doc = "Bit 3 - This is the enable bit for frm_err_int_st register."]
201 #[inline(always)]
202 pub fn frm_err(&mut self) -> FRM_ERR_W<INT_ENA_SPEC> {
203 FRM_ERR_W::new(self, 3)
204 }
205 #[doc = "Bit 4 - This is the enable bit for rxfifo_ovf_int_st register."]
206 #[inline(always)]
207 pub fn rxfifo_ovf(&mut self) -> RXFIFO_OVF_W<INT_ENA_SPEC> {
208 RXFIFO_OVF_W::new(self, 4)
209 }
210 #[doc = "Bit 5 - This is the enable bit for dsr_chg_int_st register."]
211 #[inline(always)]
212 pub fn dsr_chg(&mut self) -> DSR_CHG_W<INT_ENA_SPEC> {
213 DSR_CHG_W::new(self, 5)
214 }
215 #[doc = "Bit 6 - This is the enable bit for cts_chg_int_st register."]
216 #[inline(always)]
217 pub fn cts_chg(&mut self) -> CTS_CHG_W<INT_ENA_SPEC> {
218 CTS_CHG_W::new(self, 6)
219 }
220 #[doc = "Bit 7 - This is the enable bit for brk_det_int_st register."]
221 #[inline(always)]
222 pub fn brk_det(&mut self) -> BRK_DET_W<INT_ENA_SPEC> {
223 BRK_DET_W::new(self, 7)
224 }
225 #[doc = "Bit 8 - This is the enable bit for rxfifo_tout_int_st register."]
226 #[inline(always)]
227 pub fn rxfifo_tout(&mut self) -> RXFIFO_TOUT_W<INT_ENA_SPEC> {
228 RXFIFO_TOUT_W::new(self, 8)
229 }
230 #[doc = "Bit 9 - This is the enable bit for sw_xon_int_st register."]
231 #[inline(always)]
232 pub fn sw_xon(&mut self) -> SW_XON_W<INT_ENA_SPEC> {
233 SW_XON_W::new(self, 9)
234 }
235 #[doc = "Bit 10 - This is the enable bit for sw_xoff_int_st register."]
236 #[inline(always)]
237 pub fn sw_xoff(&mut self) -> SW_XOFF_W<INT_ENA_SPEC> {
238 SW_XOFF_W::new(self, 10)
239 }
240 #[doc = "Bit 11 - This is the enable bit for glitch_det_int_st register."]
241 #[inline(always)]
242 pub fn glitch_det(&mut self) -> GLITCH_DET_W<INT_ENA_SPEC> {
243 GLITCH_DET_W::new(self, 11)
244 }
245 #[doc = "Bit 12 - This is the enable bit for tx_brk_done_int_st register."]
246 #[inline(always)]
247 pub fn tx_brk_done(&mut self) -> TX_BRK_DONE_W<INT_ENA_SPEC> {
248 TX_BRK_DONE_W::new(self, 12)
249 }
250 #[doc = "Bit 13 - This is the enable bit for tx_brk_idle_done_int_st register."]
251 #[inline(always)]
252 pub fn tx_brk_idle_done(&mut self) -> TX_BRK_IDLE_DONE_W<INT_ENA_SPEC> {
253 TX_BRK_IDLE_DONE_W::new(self, 13)
254 }
255 #[doc = "Bit 14 - This is the enable bit for tx_done_int_st register."]
256 #[inline(always)]
257 pub fn tx_done(&mut self) -> TX_DONE_W<INT_ENA_SPEC> {
258 TX_DONE_W::new(self, 14)
259 }
260 #[doc = "Bit 18 - This is the enable bit for at_cmd_char_det_int_st register."]
261 #[inline(always)]
262 pub fn at_cmd_char_det(&mut self) -> AT_CMD_CHAR_DET_W<INT_ENA_SPEC> {
263 AT_CMD_CHAR_DET_W::new(self, 18)
264 }
265 #[doc = "Bit 19 - This is the enable bit for uart_wakeup_int_st register."]
266 #[inline(always)]
267 pub fn wakeup(&mut self) -> WAKEUP_W<INT_ENA_SPEC> {
268 WAKEUP_W::new(self, 19)
269 }
270}
271#[doc = "Interrupt enable bits\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
272pub struct INT_ENA_SPEC;
273impl crate::RegisterSpec for INT_ENA_SPEC {
274 type Ux = u32;
275}
276#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"]
277impl crate::Readable for INT_ENA_SPEC {}
278#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"]
279impl crate::Writable for INT_ENA_SPEC {
280 type Safety = crate::Unsafe;
281}
282#[doc = "`reset()` method sets INT_ENA to value 0"]
283impl crate::Resettable for INT_ENA_SPEC {}