1#[doc = "Register `INT_ST` reader"]
2pub type R = crate::R<INT_ST_SPEC>;
3#[doc = "Field `TIMER_OVF(0-3)` reader - This is the masked interrupt status bit for the TIMER%s_OVF interrupt when LEDC.INT_ENA.TIMERx_OVF is set to 1."]
4pub type TIMER_OVF_R = crate::BitReader;
5#[doc = "Field `DUTY_CHNG_END_CH(0-5)` reader - This is the masked interrupt status bit for the DUTY_CHNG_END_CH%s interrupt when LEDC.INT_ENA.DUTY_CHNG_END_CHx is set to 1."]
6pub type DUTY_CHNG_END_CH_R = crate::BitReader;
7#[doc = "Field `OVF_CNT_CH(0-5)` reader - This is the masked interrupt status bit for the LEDC.INT_RAW.OVF_CNT_CH%s interrupt when LEDC.INT_ENA.OVF_CNT_CHx is set to 1."]
8pub type OVF_CNT_CH_R = crate::BitReader;
9impl R {
10 #[doc = "This is the masked interrupt status bit for the TIMER(0-3)_OVF interrupt when LEDC.INT_ENA.TIMERx_OVF is set to 1."]
11 #[doc = ""]
12 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_OVF` field.</div>"]
13 #[inline(always)]
14 pub fn timer_ovf(&self, n: u8) -> TIMER_OVF_R {
15 #[allow(clippy::no_effect)]
16 [(); 4][n as usize];
17 TIMER_OVF_R::new(((self.bits >> n) & 1) != 0)
18 }
19 #[doc = "Iterator for array of:"]
20 #[doc = "This is the masked interrupt status bit for the TIMER(0-3)_OVF interrupt when LEDC.INT_ENA.TIMERx_OVF is set to 1."]
21 #[inline(always)]
22 pub fn timer_ovf_iter(&self) -> impl Iterator<Item = TIMER_OVF_R> + '_ {
23 (0..4).map(move |n| TIMER_OVF_R::new(((self.bits >> n) & 1) != 0))
24 }
25 #[doc = "Bit 0 - This is the masked interrupt status bit for the TIMER0_OVF interrupt when LEDC.INT_ENA.TIMERx_OVF is set to 1."]
26 #[inline(always)]
27 pub fn timer0_ovf(&self) -> TIMER_OVF_R {
28 TIMER_OVF_R::new((self.bits & 1) != 0)
29 }
30 #[doc = "Bit 1 - This is the masked interrupt status bit for the TIMER1_OVF interrupt when LEDC.INT_ENA.TIMERx_OVF is set to 1."]
31 #[inline(always)]
32 pub fn timer1_ovf(&self) -> TIMER_OVF_R {
33 TIMER_OVF_R::new(((self.bits >> 1) & 1) != 0)
34 }
35 #[doc = "Bit 2 - This is the masked interrupt status bit for the TIMER2_OVF interrupt when LEDC.INT_ENA.TIMERx_OVF is set to 1."]
36 #[inline(always)]
37 pub fn timer2_ovf(&self) -> TIMER_OVF_R {
38 TIMER_OVF_R::new(((self.bits >> 2) & 1) != 0)
39 }
40 #[doc = "Bit 3 - This is the masked interrupt status bit for the TIMER3_OVF interrupt when LEDC.INT_ENA.TIMERx_OVF is set to 1."]
41 #[inline(always)]
42 pub fn timer3_ovf(&self) -> TIMER_OVF_R {
43 TIMER_OVF_R::new(((self.bits >> 3) & 1) != 0)
44 }
45 #[doc = "This is the masked interrupt status bit for the DUTY_CHNG_END_CH(0-5) interrupt when LEDC.INT_ENA.DUTY_CHNG_END_CHx is set to 1."]
46 #[doc = ""]
47 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `DUTY_CHNG_END_CH0` field.</div>"]
48 #[inline(always)]
49 pub fn duty_chng_end_ch(&self, n: u8) -> DUTY_CHNG_END_CH_R {
50 #[allow(clippy::no_effect)]
51 [(); 6][n as usize];
52 DUTY_CHNG_END_CH_R::new(((self.bits >> (n + 4)) & 1) != 0)
53 }
54 #[doc = "Iterator for array of:"]
55 #[doc = "This is the masked interrupt status bit for the DUTY_CHNG_END_CH(0-5) interrupt when LEDC.INT_ENA.DUTY_CHNG_END_CHx is set to 1."]
56 #[inline(always)]
57 pub fn duty_chng_end_ch_iter(&self) -> impl Iterator<Item = DUTY_CHNG_END_CH_R> + '_ {
58 (0..6).map(move |n| DUTY_CHNG_END_CH_R::new(((self.bits >> (n + 4)) & 1) != 0))
59 }
60 #[doc = "Bit 4 - This is the masked interrupt status bit for the DUTY_CHNG_END_CH0 interrupt when LEDC.INT_ENA.DUTY_CHNG_END_CHx is set to 1."]
61 #[inline(always)]
62 pub fn duty_chng_end_ch0(&self) -> DUTY_CHNG_END_CH_R {
63 DUTY_CHNG_END_CH_R::new(((self.bits >> 4) & 1) != 0)
64 }
65 #[doc = "Bit 5 - This is the masked interrupt status bit for the DUTY_CHNG_END_CH1 interrupt when LEDC.INT_ENA.DUTY_CHNG_END_CHx is set to 1."]
66 #[inline(always)]
67 pub fn duty_chng_end_ch1(&self) -> DUTY_CHNG_END_CH_R {
68 DUTY_CHNG_END_CH_R::new(((self.bits >> 5) & 1) != 0)
69 }
70 #[doc = "Bit 6 - This is the masked interrupt status bit for the DUTY_CHNG_END_CH2 interrupt when LEDC.INT_ENA.DUTY_CHNG_END_CHx is set to 1."]
71 #[inline(always)]
72 pub fn duty_chng_end_ch2(&self) -> DUTY_CHNG_END_CH_R {
73 DUTY_CHNG_END_CH_R::new(((self.bits >> 6) & 1) != 0)
74 }
75 #[doc = "Bit 7 - This is the masked interrupt status bit for the DUTY_CHNG_END_CH3 interrupt when LEDC.INT_ENA.DUTY_CHNG_END_CHx is set to 1."]
76 #[inline(always)]
77 pub fn duty_chng_end_ch3(&self) -> DUTY_CHNG_END_CH_R {
78 DUTY_CHNG_END_CH_R::new(((self.bits >> 7) & 1) != 0)
79 }
80 #[doc = "Bit 8 - This is the masked interrupt status bit for the DUTY_CHNG_END_CH4 interrupt when LEDC.INT_ENA.DUTY_CHNG_END_CHx is set to 1."]
81 #[inline(always)]
82 pub fn duty_chng_end_ch4(&self) -> DUTY_CHNG_END_CH_R {
83 DUTY_CHNG_END_CH_R::new(((self.bits >> 8) & 1) != 0)
84 }
85 #[doc = "Bit 9 - This is the masked interrupt status bit for the DUTY_CHNG_END_CH5 interrupt when LEDC.INT_ENA.DUTY_CHNG_END_CHx is set to 1."]
86 #[inline(always)]
87 pub fn duty_chng_end_ch5(&self) -> DUTY_CHNG_END_CH_R {
88 DUTY_CHNG_END_CH_R::new(((self.bits >> 9) & 1) != 0)
89 }
90 #[doc = "This is the masked interrupt status bit for the LEDC.INT_RAW.OVF_CNT_CH(0-5) interrupt when LEDC.INT_ENA.OVF_CNT_CHx is set to 1."]
91 #[doc = ""]
92 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `OVF_CNT_CH0` field.</div>"]
93 #[inline(always)]
94 pub fn ovf_cnt_ch(&self, n: u8) -> OVF_CNT_CH_R {
95 #[allow(clippy::no_effect)]
96 [(); 6][n as usize];
97 OVF_CNT_CH_R::new(((self.bits >> (n + 12)) & 1) != 0)
98 }
99 #[doc = "Iterator for array of:"]
100 #[doc = "This is the masked interrupt status bit for the LEDC.INT_RAW.OVF_CNT_CH(0-5) interrupt when LEDC.INT_ENA.OVF_CNT_CHx is set to 1."]
101 #[inline(always)]
102 pub fn ovf_cnt_ch_iter(&self) -> impl Iterator<Item = OVF_CNT_CH_R> + '_ {
103 (0..6).map(move |n| OVF_CNT_CH_R::new(((self.bits >> (n + 12)) & 1) != 0))
104 }
105 #[doc = "Bit 12 - This is the masked interrupt status bit for the LEDC.INT_RAW.OVF_CNT_CH0 interrupt when LEDC.INT_ENA.OVF_CNT_CHx is set to 1."]
106 #[inline(always)]
107 pub fn ovf_cnt_ch0(&self) -> OVF_CNT_CH_R {
108 OVF_CNT_CH_R::new(((self.bits >> 12) & 1) != 0)
109 }
110 #[doc = "Bit 13 - This is the masked interrupt status bit for the LEDC.INT_RAW.OVF_CNT_CH1 interrupt when LEDC.INT_ENA.OVF_CNT_CHx is set to 1."]
111 #[inline(always)]
112 pub fn ovf_cnt_ch1(&self) -> OVF_CNT_CH_R {
113 OVF_CNT_CH_R::new(((self.bits >> 13) & 1) != 0)
114 }
115 #[doc = "Bit 14 - This is the masked interrupt status bit for the LEDC.INT_RAW.OVF_CNT_CH2 interrupt when LEDC.INT_ENA.OVF_CNT_CHx is set to 1."]
116 #[inline(always)]
117 pub fn ovf_cnt_ch2(&self) -> OVF_CNT_CH_R {
118 OVF_CNT_CH_R::new(((self.bits >> 14) & 1) != 0)
119 }
120 #[doc = "Bit 15 - This is the masked interrupt status bit for the LEDC.INT_RAW.OVF_CNT_CH3 interrupt when LEDC.INT_ENA.OVF_CNT_CHx is set to 1."]
121 #[inline(always)]
122 pub fn ovf_cnt_ch3(&self) -> OVF_CNT_CH_R {
123 OVF_CNT_CH_R::new(((self.bits >> 15) & 1) != 0)
124 }
125 #[doc = "Bit 16 - This is the masked interrupt status bit for the LEDC.INT_RAW.OVF_CNT_CH4 interrupt when LEDC.INT_ENA.OVF_CNT_CHx is set to 1."]
126 #[inline(always)]
127 pub fn ovf_cnt_ch4(&self) -> OVF_CNT_CH_R {
128 OVF_CNT_CH_R::new(((self.bits >> 16) & 1) != 0)
129 }
130 #[doc = "Bit 17 - This is the masked interrupt status bit for the LEDC.INT_RAW.OVF_CNT_CH5 interrupt when LEDC.INT_ENA.OVF_CNT_CHx is set to 1."]
131 #[inline(always)]
132 pub fn ovf_cnt_ch5(&self) -> OVF_CNT_CH_R {
133 OVF_CNT_CH_R::new(((self.bits >> 17) & 1) != 0)
134 }
135}
136#[cfg(feature = "impl-register-debug")]
137impl core::fmt::Debug for R {
138 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
139 f.debug_struct("INT_ST")
140 .field("timer0_ovf", &self.timer0_ovf())
141 .field("timer1_ovf", &self.timer1_ovf())
142 .field("timer2_ovf", &self.timer2_ovf())
143 .field("timer3_ovf", &self.timer3_ovf())
144 .field("duty_chng_end_ch0", &self.duty_chng_end_ch0())
145 .field("duty_chng_end_ch1", &self.duty_chng_end_ch1())
146 .field("duty_chng_end_ch2", &self.duty_chng_end_ch2())
147 .field("duty_chng_end_ch3", &self.duty_chng_end_ch3())
148 .field("duty_chng_end_ch4", &self.duty_chng_end_ch4())
149 .field("duty_chng_end_ch5", &self.duty_chng_end_ch5())
150 .field("ovf_cnt_ch0", &self.ovf_cnt_ch0())
151 .field("ovf_cnt_ch1", &self.ovf_cnt_ch1())
152 .field("ovf_cnt_ch2", &self.ovf_cnt_ch2())
153 .field("ovf_cnt_ch3", &self.ovf_cnt_ch3())
154 .field("ovf_cnt_ch4", &self.ovf_cnt_ch4())
155 .field("ovf_cnt_ch5", &self.ovf_cnt_ch5())
156 .finish()
157 }
158}
159#[doc = "Masked interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
160pub struct INT_ST_SPEC;
161impl crate::RegisterSpec for INT_ST_SPEC {
162 type Ux = u32;
163}
164#[doc = "`read()` method returns [`int_st::R`](R) reader structure"]
165impl crate::Readable for INT_ST_SPEC {}
166#[doc = "`reset()` method sets INT_ST to value 0"]
167impl crate::Resettable for INT_ST_SPEC {
168 const RESET_VALUE: u32 = 0;
169}