Struct esp32c6::SPI0

pub struct SPI0 { /* private fields */ }

SPI (Serial Peripheral Interface) Controller 0

Implementations

impl SPI0

pub const PTR: *const RegisterBlock = {0x60002000 as *const spi0::RegisterBlock}

Pointer to the register block

pub const fn ptr() -> *const RegisterBlock

Return the pointer to the register block

pub unsafe fn steal() -> Self

Steal an instance of this peripheral

Safety

Ensure that the new instance of the peripheral cannot be used in a way that may race with any existing instances, for example by only accessing read-only or write-only registers, or by consuming the original peripheral and using critical sections to coordinate access between multiple new instances.

Additionally, other software such as HALs may rely on only one peripheral instance existing to ensure memory safety; ensure no stolen instances are passed to such software.

Methods from Deref<Target = RegisterBlock>

pub fn cmd(&self) -> &CMD

0x00 - SPI0 FSM status register

pub fn ctrl(&self) -> &CTRL

0x08 - SPI0 control register.

pub fn ctrl1(&self) -> &CTRL1

0x0c - SPI0 control1 register.

pub fn ctrl2(&self) -> &CTRL2

0x10 - SPI0 control2 register.

pub fn clock(&self) -> &CLOCK

0x14 - SPI clock division control register.

pub fn user(&self) -> &USER

0x18 - SPI0 user register.

pub fn user1(&self) -> &USER1

0x1c - SPI0 user1 register.

pub fn user2(&self) -> &USER2

0x20 - SPI0 user2 register.

pub fn rd_status(&self) -> &RD_STATUS

0x2c - SPI0 read control register.

pub fn misc(&self) -> &MISC

0x34 - SPI0 misc register

pub fn cache_fctrl(&self) -> &CACHE_FCTRL

0x3c - SPI0 bit mode control register.

pub fn cache_sctrl(&self) -> &CACHE_SCTRL

0x40 - SPI0 external RAM control register

pub fn sram_cmd(&self) -> &SRAM_CMD

0x44 - SPI0 external RAM mode control register

pub fn sram_drd_cmd(&self) -> &SRAM_DRD_CMD

0x48 - SPI0 external RAM DDR read command control register

pub fn sram_dwr_cmd(&self) -> &SRAM_DWR_CMD

0x4c - SPI0 external RAM DDR write command control register

pub fn sram_clk(&self) -> &SRAM_CLK

0x50 - SPI0 external RAM clock control register

pub fn fsm(&self) -> &FSM

0x54 - SPI0 FSM status register

pub fn int_ena(&self) -> &INT_ENA

0xc0 - SPI0 interrupt enable register

pub fn int_clr(&self) -> &INT_CLR

0xc4 - SPI0 interrupt clear register

pub fn int_raw(&self) -> &INT_RAW

0xc8 - SPI0 interrupt raw register

pub fn int_st(&self) -> &INT_ST

0xcc - SPI0 interrupt status register

pub fn ddr(&self) -> &DDR

0xd4 - SPI0 flash DDR mode control register

pub fn spi_smem_ddr(&self) -> &SPI_SMEM_DDR

0xd8 - SPI0 external RAM DDR mode control register

pub fn spi_fmem_pms_attr(&self, n: usize) -> &SPI_FMEM_PMS_ATTR

0x100..0x110 - MSPI flash ACE section %s attribute register

pub fn spi_fmem_pms_attr_iter(&self) -> impl Iterator<Item = &SPI_FMEM_PMS_ATTR>

Iterator for array of: 0x100..0x110 - MSPI flash ACE section %s attribute register

pub fn spi_fmem_pms0_attr(&self) -> &SPI_FMEM_PMS_ATTR

0x100 - MSPI flash ACE section 0 attribute register

pub fn spi_fmem_pms1_attr(&self) -> &SPI_FMEM_PMS_ATTR

0x104 - MSPI flash ACE section 1 attribute register

pub fn spi_fmem_pms2_attr(&self) -> &SPI_FMEM_PMS_ATTR

0x108 - MSPI flash ACE section 2 attribute register

pub fn spi_fmem_pms3_attr(&self) -> &SPI_FMEM_PMS_ATTR

0x10c - MSPI flash ACE section 3 attribute register

pub fn spi_fmem_pms_addr(&self, n: usize) -> &SPI_FMEM_PMS_ADDR

0x110..0x120 - SPI1 flash ACE section %s start address register

pub fn spi_fmem_pms_addr_iter(&self) -> impl Iterator<Item = &SPI_FMEM_PMS_ADDR>

Iterator for array of: 0x110..0x120 - SPI1 flash ACE section %s start address register

pub fn spi_fmem_pms0_addr(&self) -> &SPI_FMEM_PMS_ADDR

0x110 - SPI1 flash ACE section 0 start address register

pub fn spi_fmem_pms1_addr(&self) -> &SPI_FMEM_PMS_ADDR

0x114 - SPI1 flash ACE section 1 start address register

pub fn spi_fmem_pms2_addr(&self) -> &SPI_FMEM_PMS_ADDR

0x118 - SPI1 flash ACE section 2 start address register

pub fn spi_fmem_pms3_addr(&self) -> &SPI_FMEM_PMS_ADDR

0x11c - SPI1 flash ACE section 3 start address register

pub fn spi_fmem_pms_size(&self, n: usize) -> &SPI_FMEM_PMS_SIZE

0x120..0x130 - SPI1 flash ACE section %s start address register

pub fn spi_fmem_pms_size_iter(&self) -> impl Iterator<Item = &SPI_FMEM_PMS_SIZE>

Iterator for array of: 0x120..0x130 - SPI1 flash ACE section %s start address register

pub fn spi_fmem_pms0_size(&self) -> &SPI_FMEM_PMS_SIZE

0x120 - SPI1 flash ACE section 0 start address register

pub fn spi_fmem_pms1_size(&self) -> &SPI_FMEM_PMS_SIZE

0x124 - SPI1 flash ACE section 1 start address register

pub fn spi_fmem_pms2_size(&self) -> &SPI_FMEM_PMS_SIZE

0x128 - SPI1 flash ACE section 2 start address register

pub fn spi_fmem_pms3_size(&self) -> &SPI_FMEM_PMS_SIZE

0x12c - SPI1 flash ACE section 3 start address register

pub fn spi_smem_pms_attr(&self, n: usize) -> &SPI_SMEM_PMS_ATTR

0x130..0x140 - SPI1 flash ACE section %s start address register

pub fn spi_smem_pms_attr_iter(&self) -> impl Iterator<Item = &SPI_SMEM_PMS_ATTR>

Iterator for array of: 0x130..0x140 - SPI1 flash ACE section %s start address register

pub fn spi_smem_pms0_attr(&self) -> &SPI_SMEM_PMS_ATTR

0x130 - SPI1 flash ACE section 0 start address register

pub fn spi_smem_pms1_attr(&self) -> &SPI_SMEM_PMS_ATTR

0x134 - SPI1 flash ACE section 1 start address register

pub fn spi_smem_pms2_attr(&self) -> &SPI_SMEM_PMS_ATTR

0x138 - SPI1 flash ACE section 2 start address register

pub fn spi_smem_pms3_attr(&self) -> &SPI_SMEM_PMS_ATTR

0x13c - SPI1 flash ACE section 3 start address register

pub fn spi_smem_pms_addr(&self, n: usize) -> &SPI_SMEM_PMS_ADDR

0x140..0x150 - SPI1 external RAM ACE section %s start address register

pub fn spi_smem_pms_addr_iter(&self) -> impl Iterator<Item = &SPI_SMEM_PMS_ADDR>

Iterator for array of: 0x140..0x150 - SPI1 external RAM ACE section %s start address register

pub fn spi_smem_pms0_addr(&self) -> &SPI_SMEM_PMS_ADDR

0x140 - SPI1 external RAM ACE section 0 start address register

pub fn spi_smem_pms1_addr(&self) -> &SPI_SMEM_PMS_ADDR

0x144 - SPI1 external RAM ACE section 1 start address register

pub fn spi_smem_pms2_addr(&self) -> &SPI_SMEM_PMS_ADDR

0x148 - SPI1 external RAM ACE section 2 start address register

pub fn spi_smem_pms3_addr(&self) -> &SPI_SMEM_PMS_ADDR

0x14c - SPI1 external RAM ACE section 3 start address register

pub fn spi_smem_pms_size(&self, n: usize) -> &SPI_SMEM_PMS_SIZE

0x150..0x160 - SPI1 external RAM ACE section %s start address register

pub fn spi_smem_pms_size_iter(&self) -> impl Iterator<Item = &SPI_SMEM_PMS_SIZE>

Iterator for array of: 0x150..0x160 - SPI1 external RAM ACE section %s start address register

pub fn spi_smem_pms0_size(&self) -> &SPI_SMEM_PMS_SIZE

0x150 - SPI1 external RAM ACE section 0 start address register

pub fn spi_smem_pms1_size(&self) -> &SPI_SMEM_PMS_SIZE

0x154 - SPI1 external RAM ACE section 1 start address register

pub fn spi_smem_pms2_size(&self) -> &SPI_SMEM_PMS_SIZE

0x158 - SPI1 external RAM ACE section 2 start address register

pub fn spi_smem_pms3_size(&self) -> &SPI_SMEM_PMS_SIZE

0x15c - SPI1 external RAM ACE section 3 start address register

pub fn pms_reject(&self) -> &PMS_REJECT

0x164 - SPI1 access reject register

pub fn ecc_ctrl(&self) -> &ECC_CTRL

0x168 - MSPI ECC control register

pub fn ecc_err_addr(&self) -> &ECC_ERR_ADDR

0x16c - MSPI ECC error address register

pub fn axi_err_addr(&self) -> &AXI_ERR_ADDR

0x170 - SPI0 AXI request error address.

pub fn spi_smem_ecc_ctrl(&self) -> &SPI_SMEM_ECC_CTRL

0x174 - MSPI ECC control register

pub fn timing_cali(&self) -> &TIMING_CALI

0x180 - SPI0 flash timing calibration register

pub fn din_mode(&self) -> &DIN_MODE

0x184 - MSPI flash input timing delay mode control register

pub fn din_num(&self) -> &DIN_NUM

0x188 - MSPI flash input timing delay number control register

pub fn dout_mode(&self) -> &DOUT_MODE

0x18c - MSPI flash output timing adjustment control register

pub fn spi_smem_timing_cali(&self) -> &SPI_SMEM_TIMING_CALI

0x190 - MSPI external RAM timing calibration register

pub fn spi_smem_din_mode(&self) -> &SPI_SMEM_DIN_MODE

0x194 - MSPI external RAM input timing delay mode control register

pub fn spi_smem_din_num(&self) -> &SPI_SMEM_DIN_NUM

0x198 - MSPI external RAM input timing delay number control register

pub fn spi_smem_dout_mode(&self) -> &SPI_SMEM_DOUT_MODE

0x19c - MSPI external RAM output timing adjustment control register

pub fn spi_smem_ac(&self) -> &SPI_SMEM_AC

0x1a0 - MSPI external RAM ECC and SPI CS timing control register

pub fn clock_gate(&self) -> &CLOCK_GATE

0x200 - SPI0 clock gate register

pub fn xts_plain_base(&self) -> &XTS_PLAIN_BASE

0x300 - The base address of the memory that stores plaintext in Manual Encryption

pub fn xts_linesize(&self) -> &XTS_LINESIZE

0x340 - Manual Encryption Line-Size register

pub fn xts_destination(&self) -> &XTS_DESTINATION

0x344 - Manual Encryption destination register

pub fn xts_physical_address(&self) -> &XTS_PHYSICAL_ADDRESS

0x348 - Manual Encryption physical address register

pub fn xts_trigger(&self) -> &XTS_TRIGGER

0x34c - Manual Encryption physical address register

pub fn xts_release(&self) -> &XTS_RELEASE

0x350 - Manual Encryption physical address register

pub fn xts_destroy(&self) -> &XTS_DESTROY

0x354 - Manual Encryption physical address register

pub fn xts_state(&self) -> &XTS_STATE

0x358 - Manual Encryption physical address register

pub fn xts_date(&self) -> &XTS_DATE

0x35c - Manual Encryption version register

pub fn mmu_item_content(&self) -> &MMU_ITEM_CONTENT

0x37c - MSPI-MMU item content register

pub fn mmu_item_index(&self) -> &MMU_ITEM_INDEX

0x380 - MSPI-MMU item index register

pub fn mmu_power_ctrl(&self) -> &MMU_POWER_CTRL

0x384 - MSPI MMU power control register

pub fn dpa_ctrl(&self) -> &DPA_CTRL

0x388 - SPI memory cryption DPA register

pub fn registerrnd_eco_high(&self) -> &REGISTERRND_ECO_HIGH

0x3f0 - MSPI ECO high register

pub fn registerrnd_eco_low(&self) -> &REGISTERRND_ECO_LOW

0x3f4 - MSPI ECO low register

pub fn date(&self) -> &DATE

0x3fc - SPI0 version control register

Trait Implementations

impl Debug for SPI0

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Deref for SPI0

type Target = RegisterBlock

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl Send for SPI0