Module clk_conf

UART core clock configuration

Structs

CLK_CONF_SPEC

UART core clock configuration

Type Aliases

R

Register CLK_CONF reader

RST_CORE_R

Field RST_CORE reader - Write 1 then write 0 to this bit to reset UART Tx/Rx.

RST_CORE_W

Field RST_CORE writer - Write 1 then write 0 to this bit to reset UART Tx/Rx.

RX_RST_CORE_R

Field RX_RST_CORE reader - Write 1 then write 0 to this bit to reset UART Rx.

RX_RST_CORE_W

Field RX_RST_CORE writer - Write 1 then write 0 to this bit to reset UART Rx.

RX_SCLK_EN_R

Field RX_SCLK_EN reader - Set this bit to enable UART Rx clock.

RX_SCLK_EN_W

Field RX_SCLK_EN writer - Set this bit to enable UART Rx clock.

SCLK_DIV_A_R

Field SCLK_DIV_A reader - The numerator of the frequency divider factor.

SCLK_DIV_A_W

Field SCLK_DIV_A writer - The numerator of the frequency divider factor.

SCLK_DIV_B_R

Field SCLK_DIV_B reader - The denominator of the frequency divider factor.

SCLK_DIV_B_W

Field SCLK_DIV_B writer - The denominator of the frequency divider factor.

SCLK_DIV_NUM_R

Field SCLK_DIV_NUM reader - The integral part of the frequency divider factor.

SCLK_DIV_NUM_W

Field SCLK_DIV_NUM writer - The integral part of the frequency divider factor.

SCLK_EN_R

Field SCLK_EN reader - Set this bit to enable UART Tx/Rx clock.

SCLK_EN_W

Field SCLK_EN writer - Set this bit to enable UART Tx/Rx clock.

SCLK_SEL_R

Field SCLK_SEL reader - UART clock source select. 1: 80Mhz. 2: 8Mhz. 3: XTAL.

SCLK_SEL_W

Field SCLK_SEL writer - UART clock source select. 1: 80Mhz. 2: 8Mhz. 3: XTAL.

TX_RST_CORE_R

Field TX_RST_CORE reader - Write 1 then write 0 to this bit to reset UART Tx.

TX_RST_CORE_W

Field TX_RST_CORE writer - Write 1 then write 0 to this bit to reset UART Tx.

TX_SCLK_EN_R

Field TX_SCLK_EN reader - Set this bit to enable UART Tx clock.

TX_SCLK_EN_W

Field TX_SCLK_EN writer - Set this bit to enable UART Tx clock.

W

Register CLK_CONF writer