Struct esp32c6::gpio_sd::RegisterBlock
source · #[repr(C)]pub struct RegisterBlock {Show 14 fields
pub sigmadelta: [SIGMADELTA; 4],
pub clock_gate: CLOCK_GATE,
pub sigmadelta_misc: SIGMADELTA_MISC,
pub glitch_filter_ch: [GLITCH_FILTER_CH; 8],
pub etm_event_ch_cfg: [ETM_EVENT_CH_CFG; 8],
pub etm_task_p0_cfg: ETM_TASK_P0_CFG,
pub etm_task_p1_cfg: ETM_TASK_P1_CFG,
pub etm_task_p2_cfg: ETM_TASK_P2_CFG,
pub etm_task_p3_cfg: ETM_TASK_P3_CFG,
pub etm_task_p4_cfg: ETM_TASK_P4_CFG,
pub etm_task_p5_cfg: ETM_TASK_P5_CFG,
pub etm_task_p6_cfg: ETM_TASK_P6_CFG,
pub etm_task_p7_cfg: ETM_TASK_P7_CFG,
pub version: VERSION,
/* private fields */
}Expand description
Register block
Fields§
§sigmadelta: [SIGMADELTA; 4]0x00..0x10 - Duty Cycle Configure Register of SDM%s
clock_gate: CLOCK_GATE0x20 - Clock Gating Configure Register
sigmadelta_misc: SIGMADELTA_MISC0x24 - MISC Register
glitch_filter_ch: [GLITCH_FILTER_CH; 8]0x30..0x50 - Glitch Filter Configure Register of Channel%s
etm_event_ch_cfg: [ETM_EVENT_CH_CFG; 8]0x60..0x80 - Etm Config register of Channel%s
etm_task_p0_cfg: ETM_TASK_P0_CFG0xa0 - Etm Configure Register to decide which GPIO been chosen
etm_task_p1_cfg: ETM_TASK_P1_CFG0xa4 - Etm Configure Register to decide which GPIO been chosen
etm_task_p2_cfg: ETM_TASK_P2_CFG0xa8 - Etm Configure Register to decide which GPIO been chosen
etm_task_p3_cfg: ETM_TASK_P3_CFG0xac - Etm Configure Register to decide which GPIO been chosen
etm_task_p4_cfg: ETM_TASK_P4_CFG0xb0 - Etm Configure Register to decide which GPIO been chosen
etm_task_p5_cfg: ETM_TASK_P5_CFG0xb4 - Etm Configure Register to decide which GPIO been chosen
etm_task_p6_cfg: ETM_TASK_P6_CFG0xb8 - Etm Configure Register to decide which GPIO been chosen
etm_task_p7_cfg: ETM_TASK_P7_CFG0xbc - Etm Configure Register to decide which GPIO been chosen
version: VERSION0xfc - Version Control Register