esp32c5 0.2.2

Peripheral access crate for the ESP32-C5
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58

#[doc = "Register `AHB_CONFIG` reader"]
pub type R = crate::R<AHB_CONFIG_SPEC>;
#[doc = "Register `AHB_CONFIG` writer"]
pub type W = crate::W<AHB_CONFIG_SPEC>;
#[doc = "Field `HBURST` reader - Configures the AHB burst mode. \\\\0: SIGNLE \\\\1: INCR(length not defined) \\\\2:INCR4 \\\\4:INCR8 \\\\Others:Invalid"]
pub type HBURST_R = crate::FieldReader;
#[doc = "Field `HBURST` writer - Configures the AHB burst mode. \\\\0: SIGNLE \\\\1: INCR(length not defined) \\\\2:INCR4 \\\\4:INCR8 \\\\Others:Invalid"]
pub type HBURST_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `MAX_INCR` reader - Configures the maximum burst length for INCR mode"]
pub type MAX_INCR_R = crate::FieldReader;
#[doc = "Field `MAX_INCR` writer - Configures the maximum burst length for INCR mode"]
pub type MAX_INCR_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
impl R {
    #[doc = "Bits 0:2 - Configures the AHB burst mode. \\\\0: SIGNLE \\\\1: INCR(length not defined) \\\\2:INCR4 \\\\4:INCR8 \\\\Others:Invalid"]
    #[inline(always)]
    pub fn hburst(&self) -> HBURST_R {
        HBURST_R::new((self.bits & 7) as u8)
    }
    #[doc = "Bits 3:5 - Configures the maximum burst length for INCR mode"]
    #[inline(always)]
    pub fn max_incr(&self) -> MAX_INCR_R {
        MAX_INCR_R::new(((self.bits >> 3) & 7) as u8)
    }
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("AHB_CONFIG")
            .field("hburst", &self.hburst())
            .field("max_incr", &self.max_incr())
            .finish()
    }
}
impl W {
    #[doc = "Bits 0:2 - Configures the AHB burst mode. \\\\0: SIGNLE \\\\1: INCR(length not defined) \\\\2:INCR4 \\\\4:INCR8 \\\\Others:Invalid"]
    #[inline(always)]
    pub fn hburst(&mut self) -> HBURST_W<'_, AHB_CONFIG_SPEC> {
        HBURST_W::new(self, 0)
    }
    #[doc = "Bits 3:5 - Configures the maximum burst length for INCR mode"]
    #[inline(always)]
    pub fn max_incr(&mut self) -> MAX_INCR_W<'_, AHB_CONFIG_SPEC> {
        MAX_INCR_W::new(self, 3)
    }
}
#[doc = "AHB config register\n\nYou can [`read`](crate::Reg::read) this register and get [`ahb_config::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahb_config::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AHB_CONFIG_SPEC;
impl crate::RegisterSpec for AHB_CONFIG_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [`ahb_config::R`](R) reader structure"]
impl crate::Readable for AHB_CONFIG_SPEC {}
#[doc = "`write(|w| ..)` method takes [`ahb_config::W`](W) writer structure"]
impl crate::Writable for AHB_CONFIG_SPEC {
    type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets AHB_CONFIG to value 0"]
impl crate::Resettable for AHB_CONFIG_SPEC {}