#[doc = "Register `CLK_CONF1` reader"]
pub type R = crate::R<CLK_CONF1_SPEC>;
#[doc = "Register `CLK_CONF1` writer"]
pub type W = crate::W<CLK_CONF1_SPEC>;
#[doc = "Field `CLK_WIFIBB_22M_EN` reader - "]
pub type CLK_WIFIBB_22M_EN_R = crate::BitReader;
#[doc = "Field `CLK_WIFIBB_22M_EN` writer - "]
pub type CLK_WIFIBB_22M_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_WIFIBB_40M_EN` reader - "]
pub type CLK_WIFIBB_40M_EN_R = crate::BitReader;
#[doc = "Field `CLK_WIFIBB_40M_EN` writer - "]
pub type CLK_WIFIBB_40M_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_WIFIBB_44M_EN` reader - "]
pub type CLK_WIFIBB_44M_EN_R = crate::BitReader;
#[doc = "Field `CLK_WIFIBB_44M_EN` writer - "]
pub type CLK_WIFIBB_44M_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_WIFIBB_80M_EN` reader - "]
pub type CLK_WIFIBB_80M_EN_R = crate::BitReader;
#[doc = "Field `CLK_WIFIBB_80M_EN` writer - "]
pub type CLK_WIFIBB_80M_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_WIFIBB_40X_EN` reader - "]
pub type CLK_WIFIBB_40X_EN_R = crate::BitReader;
#[doc = "Field `CLK_WIFIBB_40X_EN` writer - "]
pub type CLK_WIFIBB_40X_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_WIFIBB_80X_EN` reader - "]
pub type CLK_WIFIBB_80X_EN_R = crate::BitReader;
#[doc = "Field `CLK_WIFIBB_80X_EN` writer - "]
pub type CLK_WIFIBB_80X_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_WIFIBB_40X1_EN` reader - "]
pub type CLK_WIFIBB_40X1_EN_R = crate::BitReader;
#[doc = "Field `CLK_WIFIBB_40X1_EN` writer - "]
pub type CLK_WIFIBB_40X1_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_WIFIBB_80X1_EN` reader - "]
pub type CLK_WIFIBB_80X1_EN_R = crate::BitReader;
#[doc = "Field `CLK_WIFIBB_80X1_EN` writer - "]
pub type CLK_WIFIBB_80X1_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_WIFIBB_160X1_EN` reader - "]
pub type CLK_WIFIBB_160X1_EN_R = crate::BitReader;
#[doc = "Field `CLK_WIFIBB_160X1_EN` writer - "]
pub type CLK_WIFIBB_160X1_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_WIFIMAC_EN` reader - "]
pub type CLK_WIFIMAC_EN_R = crate::BitReader;
#[doc = "Field `CLK_WIFIMAC_EN` writer - "]
pub type CLK_WIFIMAC_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_WIFI_APB_EN` reader - "]
pub type CLK_WIFI_APB_EN_R = crate::BitReader;
#[doc = "Field `CLK_WIFI_APB_EN` writer - "]
pub type CLK_WIFI_APB_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_FE_20M_EN` reader - "]
pub type CLK_FE_20M_EN_R = crate::BitReader;
#[doc = "Field `CLK_FE_20M_EN` writer - "]
pub type CLK_FE_20M_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_FE_40M_EN` reader - "]
pub type CLK_FE_40M_EN_R = crate::BitReader;
#[doc = "Field `CLK_FE_40M_EN` writer - "]
pub type CLK_FE_40M_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_FE_80M_EN` reader - "]
pub type CLK_FE_80M_EN_R = crate::BitReader;
#[doc = "Field `CLK_FE_80M_EN` writer - "]
pub type CLK_FE_80M_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_FE_160M_EN` reader - "]
pub type CLK_FE_160M_EN_R = crate::BitReader;
#[doc = "Field `CLK_FE_160M_EN` writer - "]
pub type CLK_FE_160M_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_FE_APB_EN` reader - "]
pub type CLK_FE_APB_EN_R = crate::BitReader;
#[doc = "Field `CLK_FE_APB_EN` writer - "]
pub type CLK_FE_APB_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_BT_APB_EN` reader - "]
pub type CLK_BT_APB_EN_R = crate::BitReader;
#[doc = "Field `CLK_BT_APB_EN` writer - "]
pub type CLK_BT_APB_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_BTBB_EN` reader - "]
pub type CLK_BTBB_EN_R = crate::BitReader;
#[doc = "Field `CLK_BTBB_EN` writer - "]
pub type CLK_BTBB_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_BTMAC_EN` reader - "]
pub type CLK_BTMAC_EN_R = crate::BitReader;
#[doc = "Field `CLK_BTMAC_EN` writer - "]
pub type CLK_BTMAC_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_FE_PWDET_ADC_EN` reader - "]
pub type CLK_FE_PWDET_ADC_EN_R = crate::BitReader;
#[doc = "Field `CLK_FE_PWDET_ADC_EN` writer - "]
pub type CLK_FE_PWDET_ADC_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_FE_ADC_EN` reader - "]
pub type CLK_FE_ADC_EN_R = crate::BitReader;
#[doc = "Field `CLK_FE_ADC_EN` writer - "]
pub type CLK_FE_ADC_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_FE_DAC_EN` reader - "]
pub type CLK_FE_DAC_EN_R = crate::BitReader;
#[doc = "Field `CLK_FE_DAC_EN` writer - "]
pub type CLK_FE_DAC_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn clk_wifibb_22m_en(&self) -> CLK_WIFIBB_22M_EN_R {
CLK_WIFIBB_22M_EN_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn clk_wifibb_40m_en(&self) -> CLK_WIFIBB_40M_EN_R {
CLK_WIFIBB_40M_EN_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn clk_wifibb_44m_en(&self) -> CLK_WIFIBB_44M_EN_R {
CLK_WIFIBB_44M_EN_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn clk_wifibb_80m_en(&self) -> CLK_WIFIBB_80M_EN_R {
CLK_WIFIBB_80M_EN_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn clk_wifibb_40x_en(&self) -> CLK_WIFIBB_40X_EN_R {
CLK_WIFIBB_40X_EN_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn clk_wifibb_80x_en(&self) -> CLK_WIFIBB_80X_EN_R {
CLK_WIFIBB_80X_EN_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn clk_wifibb_40x1_en(&self) -> CLK_WIFIBB_40X1_EN_R {
CLK_WIFIBB_40X1_EN_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn clk_wifibb_80x1_en(&self) -> CLK_WIFIBB_80X1_EN_R {
CLK_WIFIBB_80X1_EN_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn clk_wifibb_160x1_en(&self) -> CLK_WIFIBB_160X1_EN_R {
CLK_WIFIBB_160X1_EN_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn clk_wifimac_en(&self) -> CLK_WIFIMAC_EN_R {
CLK_WIFIMAC_EN_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn clk_wifi_apb_en(&self) -> CLK_WIFI_APB_EN_R {
CLK_WIFI_APB_EN_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn clk_fe_20m_en(&self) -> CLK_FE_20M_EN_R {
CLK_FE_20M_EN_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn clk_fe_40m_en(&self) -> CLK_FE_40M_EN_R {
CLK_FE_40M_EN_R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13"]
#[inline(always)]
pub fn clk_fe_80m_en(&self) -> CLK_FE_80M_EN_R {
CLK_FE_80M_EN_R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn clk_fe_160m_en(&self) -> CLK_FE_160M_EN_R {
CLK_FE_160M_EN_R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn clk_fe_apb_en(&self) -> CLK_FE_APB_EN_R {
CLK_FE_APB_EN_R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn clk_bt_apb_en(&self) -> CLK_BT_APB_EN_R {
CLK_BT_APB_EN_R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17"]
#[inline(always)]
pub fn clk_btbb_en(&self) -> CLK_BTBB_EN_R {
CLK_BTBB_EN_R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18"]
#[inline(always)]
pub fn clk_btmac_en(&self) -> CLK_BTMAC_EN_R {
CLK_BTMAC_EN_R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19"]
#[inline(always)]
pub fn clk_fe_pwdet_adc_en(&self) -> CLK_FE_PWDET_ADC_EN_R {
CLK_FE_PWDET_ADC_EN_R::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20"]
#[inline(always)]
pub fn clk_fe_adc_en(&self) -> CLK_FE_ADC_EN_R {
CLK_FE_ADC_EN_R::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21"]
#[inline(always)]
pub fn clk_fe_dac_en(&self) -> CLK_FE_DAC_EN_R {
CLK_FE_DAC_EN_R::new(((self.bits >> 21) & 1) != 0)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CLK_CONF1")
.field("clk_wifibb_22m_en", &self.clk_wifibb_22m_en())
.field("clk_wifibb_40m_en", &self.clk_wifibb_40m_en())
.field("clk_wifibb_44m_en", &self.clk_wifibb_44m_en())
.field("clk_wifibb_80m_en", &self.clk_wifibb_80m_en())
.field("clk_wifibb_40x_en", &self.clk_wifibb_40x_en())
.field("clk_wifibb_80x_en", &self.clk_wifibb_80x_en())
.field("clk_wifibb_40x1_en", &self.clk_wifibb_40x1_en())
.field("clk_wifibb_80x1_en", &self.clk_wifibb_80x1_en())
.field("clk_wifibb_160x1_en", &self.clk_wifibb_160x1_en())
.field("clk_wifimac_en", &self.clk_wifimac_en())
.field("clk_wifi_apb_en", &self.clk_wifi_apb_en())
.field("clk_fe_20m_en", &self.clk_fe_20m_en())
.field("clk_fe_40m_en", &self.clk_fe_40m_en())
.field("clk_fe_80m_en", &self.clk_fe_80m_en())
.field("clk_fe_160m_en", &self.clk_fe_160m_en())
.field("clk_fe_apb_en", &self.clk_fe_apb_en())
.field("clk_bt_apb_en", &self.clk_bt_apb_en())
.field("clk_btbb_en", &self.clk_btbb_en())
.field("clk_btmac_en", &self.clk_btmac_en())
.field("clk_fe_pwdet_adc_en", &self.clk_fe_pwdet_adc_en())
.field("clk_fe_adc_en", &self.clk_fe_adc_en())
.field("clk_fe_dac_en", &self.clk_fe_dac_en())
.finish()
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
pub fn clk_wifibb_22m_en(&mut self) -> CLK_WIFIBB_22M_EN_W<'_, CLK_CONF1_SPEC> {
CLK_WIFIBB_22M_EN_W::new(self, 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn clk_wifibb_40m_en(&mut self) -> CLK_WIFIBB_40M_EN_W<'_, CLK_CONF1_SPEC> {
CLK_WIFIBB_40M_EN_W::new(self, 1)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn clk_wifibb_44m_en(&mut self) -> CLK_WIFIBB_44M_EN_W<'_, CLK_CONF1_SPEC> {
CLK_WIFIBB_44M_EN_W::new(self, 2)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn clk_wifibb_80m_en(&mut self) -> CLK_WIFIBB_80M_EN_W<'_, CLK_CONF1_SPEC> {
CLK_WIFIBB_80M_EN_W::new(self, 3)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn clk_wifibb_40x_en(&mut self) -> CLK_WIFIBB_40X_EN_W<'_, CLK_CONF1_SPEC> {
CLK_WIFIBB_40X_EN_W::new(self, 4)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn clk_wifibb_80x_en(&mut self) -> CLK_WIFIBB_80X_EN_W<'_, CLK_CONF1_SPEC> {
CLK_WIFIBB_80X_EN_W::new(self, 5)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn clk_wifibb_40x1_en(&mut self) -> CLK_WIFIBB_40X1_EN_W<'_, CLK_CONF1_SPEC> {
CLK_WIFIBB_40X1_EN_W::new(self, 6)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn clk_wifibb_80x1_en(&mut self) -> CLK_WIFIBB_80X1_EN_W<'_, CLK_CONF1_SPEC> {
CLK_WIFIBB_80X1_EN_W::new(self, 7)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn clk_wifibb_160x1_en(&mut self) -> CLK_WIFIBB_160X1_EN_W<'_, CLK_CONF1_SPEC> {
CLK_WIFIBB_160X1_EN_W::new(self, 8)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn clk_wifimac_en(&mut self) -> CLK_WIFIMAC_EN_W<'_, CLK_CONF1_SPEC> {
CLK_WIFIMAC_EN_W::new(self, 9)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn clk_wifi_apb_en(&mut self) -> CLK_WIFI_APB_EN_W<'_, CLK_CONF1_SPEC> {
CLK_WIFI_APB_EN_W::new(self, 10)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn clk_fe_20m_en(&mut self) -> CLK_FE_20M_EN_W<'_, CLK_CONF1_SPEC> {
CLK_FE_20M_EN_W::new(self, 11)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn clk_fe_40m_en(&mut self) -> CLK_FE_40M_EN_W<'_, CLK_CONF1_SPEC> {
CLK_FE_40M_EN_W::new(self, 12)
}
#[doc = "Bit 13"]
#[inline(always)]
pub fn clk_fe_80m_en(&mut self) -> CLK_FE_80M_EN_W<'_, CLK_CONF1_SPEC> {
CLK_FE_80M_EN_W::new(self, 13)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn clk_fe_160m_en(&mut self) -> CLK_FE_160M_EN_W<'_, CLK_CONF1_SPEC> {
CLK_FE_160M_EN_W::new(self, 14)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn clk_fe_apb_en(&mut self) -> CLK_FE_APB_EN_W<'_, CLK_CONF1_SPEC> {
CLK_FE_APB_EN_W::new(self, 15)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn clk_bt_apb_en(&mut self) -> CLK_BT_APB_EN_W<'_, CLK_CONF1_SPEC> {
CLK_BT_APB_EN_W::new(self, 16)
}
#[doc = "Bit 17"]
#[inline(always)]
pub fn clk_btbb_en(&mut self) -> CLK_BTBB_EN_W<'_, CLK_CONF1_SPEC> {
CLK_BTBB_EN_W::new(self, 17)
}
#[doc = "Bit 18"]
#[inline(always)]
pub fn clk_btmac_en(&mut self) -> CLK_BTMAC_EN_W<'_, CLK_CONF1_SPEC> {
CLK_BTMAC_EN_W::new(self, 18)
}
#[doc = "Bit 19"]
#[inline(always)]
pub fn clk_fe_pwdet_adc_en(&mut self) -> CLK_FE_PWDET_ADC_EN_W<'_, CLK_CONF1_SPEC> {
CLK_FE_PWDET_ADC_EN_W::new(self, 19)
}
#[doc = "Bit 20"]
#[inline(always)]
pub fn clk_fe_adc_en(&mut self) -> CLK_FE_ADC_EN_W<'_, CLK_CONF1_SPEC> {
CLK_FE_ADC_EN_W::new(self, 20)
}
#[doc = "Bit 21"]
#[inline(always)]
pub fn clk_fe_dac_en(&mut self) -> CLK_FE_DAC_EN_W<'_, CLK_CONF1_SPEC> {
CLK_FE_DAC_EN_W::new(self, 21)
}
}
#[doc = "CLK_CONF1\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_conf1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_conf1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CLK_CONF1_SPEC;
impl crate::RegisterSpec for CLK_CONF1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`clk_conf1::R`](R) reader structure"]
impl crate::Readable for CLK_CONF1_SPEC {}
#[doc = "`write(|w| ..)` method takes [`clk_conf1::W`](W) writer structure"]
impl crate::Writable for CLK_CONF1_SPEC {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CLK_CONF1 to value 0"]
impl crate::Resettable for CLK_CONF1_SPEC {}