esp32c5 0.2.1

Peripheral access crate for the ESP32-C5
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60

#[doc = "Register `CACHE_ACS_FAIL_INT_ENA` reader"]
pub type R = crate::R<CACHE_ACS_FAIL_INT_ENA_SPEC>;
#[doc = "Register `CACHE_ACS_FAIL_INT_ENA` writer"]
pub type W = crate::W<CACHE_ACS_FAIL_INT_ENA_SPEC>;
#[doc = "Field `ICACHE2_FAIL_INT_ENA` reader - Reserved"]
pub type ICACHE2_FAIL_INT_ENA_R = crate::BitReader;
#[doc = "Field `ICACHE2_FAIL_INT_ENA` writer - Reserved"]
pub type ICACHE2_FAIL_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CACHE_FAIL_INT_ENA` reader - The bit is used to enable interrupt of access fail that occurs in DCache due to cpu accesses DCache."]
pub type CACHE_FAIL_INT_ENA_R = crate::BitReader;
#[doc = "Field `CACHE_FAIL_INT_ENA` writer - The bit is used to enable interrupt of access fail that occurs in DCache due to cpu accesses DCache."]
pub type CACHE_FAIL_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    #[doc = "Bit 2 - Reserved"]
    #[inline(always)]
    pub fn icache2_fail_int_ena(&self) -> ICACHE2_FAIL_INT_ENA_R {
        ICACHE2_FAIL_INT_ENA_R::new(((self.bits >> 2) & 1) != 0)
    }
    #[doc = "Bit 4 - The bit is used to enable interrupt of access fail that occurs in DCache due to cpu accesses DCache."]
    #[inline(always)]
    pub fn cache_fail_int_ena(&self) -> CACHE_FAIL_INT_ENA_R {
        CACHE_FAIL_INT_ENA_R::new(((self.bits >> 4) & 1) != 0)
    }
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("CACHE_ACS_FAIL_INT_ENA")
            .field("icache2_fail_int_ena", &self.icache2_fail_int_ena())
            .field("cache_fail_int_ena", &self.cache_fail_int_ena())
            .finish()
    }
}
impl W {
    #[doc = "Bit 2 - Reserved"]
    #[inline(always)]
    pub fn icache2_fail_int_ena(
        &mut self,
    ) -> ICACHE2_FAIL_INT_ENA_W<'_, CACHE_ACS_FAIL_INT_ENA_SPEC> {
        ICACHE2_FAIL_INT_ENA_W::new(self, 2)
    }
    #[doc = "Bit 4 - The bit is used to enable interrupt of access fail that occurs in DCache due to cpu accesses DCache."]
    #[inline(always)]
    pub fn cache_fail_int_ena(&mut self) -> CACHE_FAIL_INT_ENA_W<'_, CACHE_ACS_FAIL_INT_ENA_SPEC> {
        CACHE_FAIL_INT_ENA_W::new(self, 4)
    }
}
#[doc = "Cache Access Fail Interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_acs_fail_int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_acs_fail_int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CACHE_ACS_FAIL_INT_ENA_SPEC;
impl crate::RegisterSpec for CACHE_ACS_FAIL_INT_ENA_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [`cache_acs_fail_int_ena::R`](R) reader structure"]
impl crate::Readable for CACHE_ACS_FAIL_INT_ENA_SPEC {}
#[doc = "`write(|w| ..)` method takes [`cache_acs_fail_int_ena::W`](W) writer structure"]
impl crate::Writable for CACHE_ACS_FAIL_INT_ENA_SPEC {
    type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CACHE_ACS_FAIL_INT_ENA to value 0"]
impl crate::Resettable for CACHE_ACS_FAIL_INT_ENA_SPEC {}