esp32c5 0.2.0

Peripheral access crate for the ESP32-C5
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

#[doc = "Register `IBUS2_ACS_NXTLVL_RD_CNT` reader"]
pub type R = crate::R<IBUS2_ACS_NXTLVL_RD_CNT_SPEC>;
#[doc = "Field `IBUS2_NXTLVL_RD_CNT` reader - The register records the number of times that ICache accesses L2-Cache due to bus2 accessing ICache2."]
pub type IBUS2_NXTLVL_RD_CNT_R = crate::FieldReader<u32>;
impl R {
    #[doc = "Bits 0:31 - The register records the number of times that ICache accesses L2-Cache due to bus2 accessing ICache2."]
    #[inline(always)]
    pub fn ibus2_nxtlvl_rd_cnt(&self) -> IBUS2_NXTLVL_RD_CNT_R {
        IBUS2_NXTLVL_RD_CNT_R::new(self.bits)
    }
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("IBUS2_ACS_NXTLVL_RD_CNT")
            .field("ibus2_nxtlvl_rd_cnt", &self.ibus2_nxtlvl_rd_cnt())
            .finish()
    }
}
#[doc = "ICache bus2 Next-Level-Access Counter register\n\nYou can [`read`](crate::Reg::read) this register and get [`ibus2_acs_nxtlvl_rd_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IBUS2_ACS_NXTLVL_RD_CNT_SPEC;
impl crate::RegisterSpec for IBUS2_ACS_NXTLVL_RD_CNT_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [`ibus2_acs_nxtlvl_rd_cnt::R`](R) reader structure"]
impl crate::Readable for IBUS2_ACS_NXTLVL_RD_CNT_SPEC {}
#[doc = "`reset()` method sets IBUS2_ACS_NXTLVL_RD_CNT to value 0"]
impl crate::Resettable for IBUS2_ACS_NXTLVL_RD_CNT_SPEC {}