esp32c3/extmem/
cache_mmu_power_ctrl.rs

1#[doc = "Register `CACHE_MMU_POWER_CTRL` reader"]
2pub type R = crate::R<CACHE_MMU_POWER_CTRL_SPEC>;
3#[doc = "Register `CACHE_MMU_POWER_CTRL` writer"]
4pub type W = crate::W<CACHE_MMU_POWER_CTRL_SPEC>;
5#[doc = "Field `CACHE_MMU_MEM_FORCE_ON` reader - The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable"]
6pub type CACHE_MMU_MEM_FORCE_ON_R = crate::BitReader;
7#[doc = "Field `CACHE_MMU_MEM_FORCE_ON` writer - The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable"]
8pub type CACHE_MMU_MEM_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CACHE_MMU_MEM_FORCE_PD` reader - The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down"]
10pub type CACHE_MMU_MEM_FORCE_PD_R = crate::BitReader;
11#[doc = "Field `CACHE_MMU_MEM_FORCE_PD` writer - The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down"]
12pub type CACHE_MMU_MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CACHE_MMU_MEM_FORCE_PU` reader - The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up"]
14pub type CACHE_MMU_MEM_FORCE_PU_R = crate::BitReader;
15#[doc = "Field `CACHE_MMU_MEM_FORCE_PU` writer - The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up"]
16pub type CACHE_MMU_MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
17impl R {
18    #[doc = "Bit 0 - The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable"]
19    #[inline(always)]
20    pub fn cache_mmu_mem_force_on(&self) -> CACHE_MMU_MEM_FORCE_ON_R {
21        CACHE_MMU_MEM_FORCE_ON_R::new((self.bits & 1) != 0)
22    }
23    #[doc = "Bit 1 - The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down"]
24    #[inline(always)]
25    pub fn cache_mmu_mem_force_pd(&self) -> CACHE_MMU_MEM_FORCE_PD_R {
26        CACHE_MMU_MEM_FORCE_PD_R::new(((self.bits >> 1) & 1) != 0)
27    }
28    #[doc = "Bit 2 - The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up"]
29    #[inline(always)]
30    pub fn cache_mmu_mem_force_pu(&self) -> CACHE_MMU_MEM_FORCE_PU_R {
31        CACHE_MMU_MEM_FORCE_PU_R::new(((self.bits >> 2) & 1) != 0)
32    }
33}
34#[cfg(feature = "impl-register-debug")]
35impl core::fmt::Debug for R {
36    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
37        f.debug_struct("CACHE_MMU_POWER_CTRL")
38            .field("cache_mmu_mem_force_on", &self.cache_mmu_mem_force_on())
39            .field("cache_mmu_mem_force_pd", &self.cache_mmu_mem_force_pd())
40            .field("cache_mmu_mem_force_pu", &self.cache_mmu_mem_force_pu())
41            .finish()
42    }
43}
44impl W {
45    #[doc = "Bit 0 - The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable"]
46    #[inline(always)]
47    pub fn cache_mmu_mem_force_on(
48        &mut self,
49    ) -> CACHE_MMU_MEM_FORCE_ON_W<CACHE_MMU_POWER_CTRL_SPEC> {
50        CACHE_MMU_MEM_FORCE_ON_W::new(self, 0)
51    }
52    #[doc = "Bit 1 - The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down"]
53    #[inline(always)]
54    pub fn cache_mmu_mem_force_pd(
55        &mut self,
56    ) -> CACHE_MMU_MEM_FORCE_PD_W<CACHE_MMU_POWER_CTRL_SPEC> {
57        CACHE_MMU_MEM_FORCE_PD_W::new(self, 1)
58    }
59    #[doc = "Bit 2 - The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up"]
60    #[inline(always)]
61    pub fn cache_mmu_mem_force_pu(
62        &mut self,
63    ) -> CACHE_MMU_MEM_FORCE_PU_W<CACHE_MMU_POWER_CTRL_SPEC> {
64        CACHE_MMU_MEM_FORCE_PU_W::new(self, 2)
65    }
66}
67#[doc = "This description will be updated in the near future.\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_mmu_power_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_mmu_power_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
68pub struct CACHE_MMU_POWER_CTRL_SPEC;
69impl crate::RegisterSpec for CACHE_MMU_POWER_CTRL_SPEC {
70    type Ux = u32;
71}
72#[doc = "`read()` method returns [`cache_mmu_power_ctrl::R`](R) reader structure"]
73impl crate::Readable for CACHE_MMU_POWER_CTRL_SPEC {}
74#[doc = "`write(|w| ..)` method takes [`cache_mmu_power_ctrl::W`](W) writer structure"]
75impl crate::Writable for CACHE_MMU_POWER_CTRL_SPEC {
76    type Safety = crate::Unsafe;
77    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
78    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
79}
80#[doc = "`reset()` method sets CACHE_MMU_POWER_CTRL to value 0x05"]
81impl crate::Resettable for CACHE_MMU_POWER_CTRL_SPEC {
82    const RESET_VALUE: u32 = 0x05;
83}
esp32c3/extmem/cache_mmu_power_ctrl.rs

esp32c3/extmem/
cache_mmu_power_ctrl.rs
