Type Alias esp32c3::extmem::core0_acs_cache_int_clr::W
source · pub type W = W<CORE0_ACS_CACHE_INT_CLR_SPEC>;
Expand description
Register CORE0_ACS_CACHE_INT_CLR
writer
Aliased Type§
struct W { /* private fields */ }
Implementations§
source§impl W
impl W
sourcepub fn core0_ibus_acs_msk_ic(
&mut self
) -> CORE0_IBUS_ACS_MSK_IC_W<'_, CORE0_ACS_CACHE_INT_CLR_SPEC>
pub fn core0_ibus_acs_msk_ic( &mut self ) -> CORE0_IBUS_ACS_MSK_IC_W<'_, CORE0_ACS_CACHE_INT_CLR_SPEC>
Bit 0 - The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access.
sourcepub fn core0_ibus_wr_ic(
&mut self
) -> CORE0_IBUS_WR_IC_W<'_, CORE0_ACS_CACHE_INT_CLR_SPEC>
pub fn core0_ibus_wr_ic( &mut self ) -> CORE0_IBUS_WR_IC_W<'_, CORE0_ACS_CACHE_INT_CLR_SPEC>
Bit 1 - The bit is used to clear interrupt by ibus trying to write icache
sourcepub fn core0_ibus_reject(
&mut self
) -> CORE0_IBUS_REJECT_W<'_, CORE0_ACS_CACHE_INT_CLR_SPEC>
pub fn core0_ibus_reject( &mut self ) -> CORE0_IBUS_REJECT_W<'_, CORE0_ACS_CACHE_INT_CLR_SPEC>
Bit 2 - The bit is used to clear interrupt by authentication fail.
sourcepub fn core0_dbus_acs_msk_ic(
&mut self
) -> CORE0_DBUS_ACS_MSK_IC_W<'_, CORE0_ACS_CACHE_INT_CLR_SPEC>
pub fn core0_dbus_acs_msk_ic( &mut self ) -> CORE0_DBUS_ACS_MSK_IC_W<'_, CORE0_ACS_CACHE_INT_CLR_SPEC>
Bit 3 - The bit is used to clear interrupt by cpu access icache while the corresponding dbus is disabled or icache is disabled which include speculative access.
sourcepub fn core0_dbus_reject(
&mut self
) -> CORE0_DBUS_REJECT_W<'_, CORE0_ACS_CACHE_INT_CLR_SPEC>
pub fn core0_dbus_reject( &mut self ) -> CORE0_DBUS_REJECT_W<'_, CORE0_ACS_CACHE_INT_CLR_SPEC>
Bit 4 - The bit is used to clear interrupt by authentication fail.
sourcepub fn core0_dbus_wr_ic(
&mut self
) -> CORE0_DBUS_WR_IC_W<'_, CORE0_ACS_CACHE_INT_CLR_SPEC>
pub fn core0_dbus_wr_ic( &mut self ) -> CORE0_DBUS_WR_IC_W<'_, CORE0_ACS_CACHE_INT_CLR_SPEC>
Bit 5 - The bit is used to clear interrupt by dbus trying to write icache