esp32c3/apb_saradc/
thres1_ctrl.rs

1#[doc = "Register `THRES1_CTRL` reader"]
2pub type R = crate::R<THRES1_CTRL_SPEC>;
3#[doc = "Register `THRES1_CTRL` writer"]
4pub type W = crate::W<THRES1_CTRL_SPEC>;
5#[doc = "Field `THRES1_CHANNEL` reader - configure thres1 to adc channel"]
6pub type THRES1_CHANNEL_R = crate::FieldReader;
7#[doc = "Field `THRES1_CHANNEL` writer - configure thres1 to adc channel"]
8pub type THRES1_CHANNEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9#[doc = "Field `THRES1_HIGH` reader - saradc thres1 monitor thres"]
10pub type THRES1_HIGH_R = crate::FieldReader<u16>;
11#[doc = "Field `THRES1_HIGH` writer - saradc thres1 monitor thres"]
12pub type THRES1_HIGH_W<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
13#[doc = "Field `THRES1_LOW` reader - saradc thres1 monitor thres"]
14pub type THRES1_LOW_R = crate::FieldReader<u16>;
15#[doc = "Field `THRES1_LOW` writer - saradc thres1 monitor thres"]
16pub type THRES1_LOW_W<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
17impl R {
18    #[doc = "Bits 0:3 - configure thres1 to adc channel"]
19    #[inline(always)]
20    pub fn thres1_channel(&self) -> THRES1_CHANNEL_R {
21        THRES1_CHANNEL_R::new((self.bits & 0x0f) as u8)
22    }
23    #[doc = "Bits 5:17 - saradc thres1 monitor thres"]
24    #[inline(always)]
25    pub fn thres1_high(&self) -> THRES1_HIGH_R {
26        THRES1_HIGH_R::new(((self.bits >> 5) & 0x1fff) as u16)
27    }
28    #[doc = "Bits 18:30 - saradc thres1 monitor thres"]
29    #[inline(always)]
30    pub fn thres1_low(&self) -> THRES1_LOW_R {
31        THRES1_LOW_R::new(((self.bits >> 18) & 0x1fff) as u16)
32    }
33}
34#[cfg(feature = "impl-register-debug")]
35impl core::fmt::Debug for R {
36    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
37        f.debug_struct("THRES1_CTRL")
38            .field("thres1_channel", &self.thres1_channel())
39            .field("thres1_high", &self.thres1_high())
40            .field("thres1_low", &self.thres1_low())
41            .finish()
42    }
43}
44impl W {
45    #[doc = "Bits 0:3 - configure thres1 to adc channel"]
46    #[inline(always)]
47    pub fn thres1_channel(&mut self) -> THRES1_CHANNEL_W<THRES1_CTRL_SPEC> {
48        THRES1_CHANNEL_W::new(self, 0)
49    }
50    #[doc = "Bits 5:17 - saradc thres1 monitor thres"]
51    #[inline(always)]
52    pub fn thres1_high(&mut self) -> THRES1_HIGH_W<THRES1_CTRL_SPEC> {
53        THRES1_HIGH_W::new(self, 5)
54    }
55    #[doc = "Bits 18:30 - saradc thres1 monitor thres"]
56    #[inline(always)]
57    pub fn thres1_low(&mut self) -> THRES1_LOW_W<THRES1_CTRL_SPEC> {
58        THRES1_LOW_W::new(self, 18)
59    }
60}
61#[doc = "digital saradc configure register\n\nYou can [`read`](crate::Reg::read) this register and get [`thres1_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`thres1_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
62pub struct THRES1_CTRL_SPEC;
63impl crate::RegisterSpec for THRES1_CTRL_SPEC {
64    type Ux = u32;
65}
66#[doc = "`read()` method returns [`thres1_ctrl::R`](R) reader structure"]
67impl crate::Readable for THRES1_CTRL_SPEC {}
68#[doc = "`write(|w| ..)` method takes [`thres1_ctrl::W`](W) writer structure"]
69impl crate::Writable for THRES1_CTRL_SPEC {
70    type Safety = crate::Unsafe;
71    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
72    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
73}
74#[doc = "`reset()` method sets THRES1_CTRL to value 0x0003_ffed"]
75impl crate::Resettable for THRES1_CTRL_SPEC {
76    const RESET_VALUE: u32 = 0x0003_ffed;
77}
esp32c3/apb_saradc/thres1_ctrl.rs

esp32c3/apb_saradc/
thres1_ctrl.rs
