esp32c3/spi2/
cmd.rs

1#[doc = "Register `CMD` reader"]
2pub type R = crate::R<CMD_SPEC>;
3#[doc = "Register `CMD` writer"]
4pub type W = crate::W<CMD_SPEC>;
5#[doc = "Field `CONF_BITLEN` reader - Define the APB cycles of SPI_CONF state. Can be configured in CONF state."]
6pub type CONF_BITLEN_R = crate::FieldReader<u32>;
7#[doc = "Field `CONF_BITLEN` writer - Define the APB cycles of SPI_CONF state. Can be configured in CONF state."]
8pub type CONF_BITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>;
9#[doc = "Field `UPDATE` reader - Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode."]
10pub type UPDATE_R = crate::BitReader;
11#[doc = "Field `UPDATE` writer - Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode."]
12pub type UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `USR` reader - User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf."]
14pub type USR_R = crate::BitReader;
15#[doc = "Field `USR` writer - User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf."]
16pub type USR_W<'a, REG> = crate::BitWriter<'a, REG>;
17impl R {
18    #[doc = "Bits 0:17 - Define the APB cycles of SPI_CONF state. Can be configured in CONF state."]
19    #[inline(always)]
20    pub fn conf_bitlen(&self) -> CONF_BITLEN_R {
21        CONF_BITLEN_R::new(self.bits & 0x0003_ffff)
22    }
23    #[doc = "Bit 23 - Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode."]
24    #[inline(always)]
25    pub fn update(&self) -> UPDATE_R {
26        UPDATE_R::new(((self.bits >> 23) & 1) != 0)
27    }
28    #[doc = "Bit 24 - User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf."]
29    #[inline(always)]
30    pub fn usr(&self) -> USR_R {
31        USR_R::new(((self.bits >> 24) & 1) != 0)
32    }
33}
34#[cfg(feature = "impl-register-debug")]
35impl core::fmt::Debug for R {
36    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
37        f.debug_struct("CMD")
38            .field("conf_bitlen", &self.conf_bitlen())
39            .field("update", &self.update())
40            .field("usr", &self.usr())
41            .finish()
42    }
43}
44impl W {
45    #[doc = "Bits 0:17 - Define the APB cycles of SPI_CONF state. Can be configured in CONF state."]
46    #[inline(always)]
47    pub fn conf_bitlen(&mut self) -> CONF_BITLEN_W<CMD_SPEC> {
48        CONF_BITLEN_W::new(self, 0)
49    }
50    #[doc = "Bit 23 - Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode."]
51    #[inline(always)]
52    pub fn update(&mut self) -> UPDATE_W<CMD_SPEC> {
53        UPDATE_W::new(self, 23)
54    }
55    #[doc = "Bit 24 - User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf."]
56    #[inline(always)]
57    pub fn usr(&mut self) -> USR_W<CMD_SPEC> {
58        USR_W::new(self, 24)
59    }
60}
61#[doc = "Command control register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
62pub struct CMD_SPEC;
63impl crate::RegisterSpec for CMD_SPEC {
64    type Ux = u32;
65}
66#[doc = "`read()` method returns [`cmd::R`](R) reader structure"]
67impl crate::Readable for CMD_SPEC {}
68#[doc = "`write(|w| ..)` method takes [`cmd::W`](W) writer structure"]
69impl crate::Writable for CMD_SPEC {
70    type Safety = crate::Unsafe;
71    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
72    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
73}
74#[doc = "`reset()` method sets CMD to value 0"]
75impl crate::Resettable for CMD_SPEC {
76    const RESET_VALUE: u32 = 0;
77}
esp32c3/spi2/cmd.rs

esp32c3/spi2/
cmd.rs
