esp32c2/uart0/
id.rs

1#[doc = "Register `ID` reader"]
2pub type R = crate::R<ID_SPEC>;
3#[doc = "Register `ID` writer"]
4pub type W = crate::W<ID_SPEC>;
5#[doc = "Field `ID` reader - This register is used to configure the uart_id."]
6pub type ID_R = crate::FieldReader<u32>;
7#[doc = "Field `ID` writer - This register is used to configure the uart_id."]
8pub type ID_W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
9#[doc = "Field `HIGH_SPEED` reader - This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers."]
10pub type HIGH_SPEED_R = crate::BitReader;
11#[doc = "Field `HIGH_SPEED` writer - This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers."]
12pub type HIGH_SPEED_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `REG_UPDATE` reader - Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done."]
14pub type REG_UPDATE_R = crate::BitReader;
15#[doc = "Field `REG_UPDATE` writer - Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done."]
16pub type REG_UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>;
17impl R {
18    #[doc = "Bits 0:29 - This register is used to configure the uart_id."]
19    #[inline(always)]
20    pub fn id(&self) -> ID_R {
21        ID_R::new(self.bits & 0x3fff_ffff)
22    }
23    #[doc = "Bit 30 - This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers."]
24    #[inline(always)]
25    pub fn high_speed(&self) -> HIGH_SPEED_R {
26        HIGH_SPEED_R::new(((self.bits >> 30) & 1) != 0)
27    }
28    #[doc = "Bit 31 - Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done."]
29    #[inline(always)]
30    pub fn reg_update(&self) -> REG_UPDATE_R {
31        REG_UPDATE_R::new(((self.bits >> 31) & 1) != 0)
32    }
33}
34#[cfg(feature = "impl-register-debug")]
35impl core::fmt::Debug for R {
36    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
37        f.debug_struct("ID")
38            .field("id", &self.id())
39            .field("high_speed", &self.high_speed())
40            .field("reg_update", &self.reg_update())
41            .finish()
42    }
43}
44impl W {
45    #[doc = "Bits 0:29 - This register is used to configure the uart_id."]
46    #[inline(always)]
47    pub fn id(&mut self) -> ID_W<ID_SPEC> {
48        ID_W::new(self, 0)
49    }
50    #[doc = "Bit 30 - This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers."]
51    #[inline(always)]
52    pub fn high_speed(&mut self) -> HIGH_SPEED_W<ID_SPEC> {
53        HIGH_SPEED_W::new(self, 30)
54    }
55    #[doc = "Bit 31 - Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done."]
56    #[inline(always)]
57    pub fn reg_update(&mut self) -> REG_UPDATE_W<ID_SPEC> {
58        REG_UPDATE_W::new(self, 31)
59    }
60}
61#[doc = "UART ID register\n\nYou can [`read`](crate::Reg::read) this register and get [`id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
62pub struct ID_SPEC;
63impl crate::RegisterSpec for ID_SPEC {
64    type Ux = u32;
65}
66#[doc = "`read()` method returns [`id::R`](R) reader structure"]
67impl crate::Readable for ID_SPEC {}
68#[doc = "`write(|w| ..)` method takes [`id::W`](W) writer structure"]
69impl crate::Writable for ID_SPEC {
70    type Safety = crate::Unsafe;
71    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
72    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
73}
74#[doc = "`reset()` method sets ID to value 0x4000_0500"]
75impl crate::Resettable for ID_SPEC {
76    const RESET_VALUE: u32 = 0x4000_0500;
77}
esp32c2/uart0/id.rs

esp32c2/uart0/
id.rs
