esp32c2/system/
perip_clk_en0.rs

1#[doc = "Register `PERIP_CLK_EN0` reader"]
2pub type R = crate::R<PERIP_CLK_EN0_SPEC>;
3#[doc = "Register `PERIP_CLK_EN0` writer"]
4pub type W = crate::W<PERIP_CLK_EN0_SPEC>;
5#[doc = "Field `SPI01_CLK_EN` reader - Set 1 to enable SPI01 clock"]
6pub type SPI01_CLK_EN_R = crate::BitReader;
7#[doc = "Field `SPI01_CLK_EN` writer - Set 1 to enable SPI01 clock"]
8pub type SPI01_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `UART_CLK_EN` reader - Set 1 to enable UART clock"]
10pub type UART_CLK_EN_R = crate::BitReader;
11#[doc = "Field `UART_CLK_EN` writer - Set 1 to enable UART clock"]
12pub type UART_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `UART1_CLK_EN` reader - Set 1 to enable UART1 clock"]
14pub type UART1_CLK_EN_R = crate::BitReader;
15#[doc = "Field `UART1_CLK_EN` writer - Set 1 to enable UART1 clock"]
16pub type UART1_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `SPI2_CLK_EN` reader - Set 1 to enable SPI2 clock"]
18pub type SPI2_CLK_EN_R = crate::BitReader;
19#[doc = "Field `SPI2_CLK_EN` writer - Set 1 to enable SPI2 clock"]
20pub type SPI2_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `I2C_EXT0_CLK_EN` reader - Set 1 to enable I2C_EXT0 clock"]
22pub type I2C_EXT0_CLK_EN_R = crate::BitReader;
23#[doc = "Field `I2C_EXT0_CLK_EN` writer - Set 1 to enable I2C_EXT0 clock"]
24pub type I2C_EXT0_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `LEDC_CLK_EN` reader - Set 1 to enable LEDC clock"]
26pub type LEDC_CLK_EN_R = crate::BitReader;
27#[doc = "Field `LEDC_CLK_EN` writer - Set 1 to enable LEDC clock"]
28pub type LEDC_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `TIMERGROUP_CLK_EN` reader - Set 1 to enable TIMERGROUP clock"]
30pub type TIMERGROUP_CLK_EN_R = crate::BitReader;
31#[doc = "Field `TIMERGROUP_CLK_EN` writer - Set 1 to enable TIMERGROUP clock"]
32pub type TIMERGROUP_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `UART_MEM_CLK_EN` reader - Set 1 to enable UART_MEM clock"]
34pub type UART_MEM_CLK_EN_R = crate::BitReader;
35#[doc = "Field `UART_MEM_CLK_EN` writer - Set 1 to enable UART_MEM clock"]
36pub type UART_MEM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `APB_SARADC_CLK_EN` reader - Set 1 to enable APB_SARADC clock"]
38pub type APB_SARADC_CLK_EN_R = crate::BitReader;
39#[doc = "Field `APB_SARADC_CLK_EN` writer - Set 1 to enable APB_SARADC clock"]
40pub type APB_SARADC_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `SYSTIMER_CLK_EN` reader - Set 1 to enable SYSTEMTIMER clock"]
42pub type SYSTIMER_CLK_EN_R = crate::BitReader;
43#[doc = "Field `SYSTIMER_CLK_EN` writer - Set 1 to enable SYSTEMTIMER clock"]
44pub type SYSTIMER_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `ADC2_ARB_CLK_EN` reader - Set 1 to enable ADC2_ARB clock"]
46pub type ADC2_ARB_CLK_EN_R = crate::BitReader;
47#[doc = "Field `ADC2_ARB_CLK_EN` writer - Set 1 to enable ADC2_ARB clock"]
48pub type ADC2_ARB_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
49impl R {
50    #[doc = "Bit 1 - Set 1 to enable SPI01 clock"]
51    #[inline(always)]
52    pub fn spi01_clk_en(&self) -> SPI01_CLK_EN_R {
53        SPI01_CLK_EN_R::new(((self.bits >> 1) & 1) != 0)
54    }
55    #[doc = "Bit 2 - Set 1 to enable UART clock"]
56    #[inline(always)]
57    pub fn uart_clk_en(&self) -> UART_CLK_EN_R {
58        UART_CLK_EN_R::new(((self.bits >> 2) & 1) != 0)
59    }
60    #[doc = "Bit 5 - Set 1 to enable UART1 clock"]
61    #[inline(always)]
62    pub fn uart1_clk_en(&self) -> UART1_CLK_EN_R {
63        UART1_CLK_EN_R::new(((self.bits >> 5) & 1) != 0)
64    }
65    #[doc = "Bit 6 - Set 1 to enable SPI2 clock"]
66    #[inline(always)]
67    pub fn spi2_clk_en(&self) -> SPI2_CLK_EN_R {
68        SPI2_CLK_EN_R::new(((self.bits >> 6) & 1) != 0)
69    }
70    #[doc = "Bit 7 - Set 1 to enable I2C_EXT0 clock"]
71    #[inline(always)]
72    pub fn i2c_ext0_clk_en(&self) -> I2C_EXT0_CLK_EN_R {
73        I2C_EXT0_CLK_EN_R::new(((self.bits >> 7) & 1) != 0)
74    }
75    #[doc = "Bit 11 - Set 1 to enable LEDC clock"]
76    #[inline(always)]
77    pub fn ledc_clk_en(&self) -> LEDC_CLK_EN_R {
78        LEDC_CLK_EN_R::new(((self.bits >> 11) & 1) != 0)
79    }
80    #[doc = "Bit 13 - Set 1 to enable TIMERGROUP clock"]
81    #[inline(always)]
82    pub fn timergroup_clk_en(&self) -> TIMERGROUP_CLK_EN_R {
83        TIMERGROUP_CLK_EN_R::new(((self.bits >> 13) & 1) != 0)
84    }
85    #[doc = "Bit 24 - Set 1 to enable UART_MEM clock"]
86    #[inline(always)]
87    pub fn uart_mem_clk_en(&self) -> UART_MEM_CLK_EN_R {
88        UART_MEM_CLK_EN_R::new(((self.bits >> 24) & 1) != 0)
89    }
90    #[doc = "Bit 28 - Set 1 to enable APB_SARADC clock"]
91    #[inline(always)]
92    pub fn apb_saradc_clk_en(&self) -> APB_SARADC_CLK_EN_R {
93        APB_SARADC_CLK_EN_R::new(((self.bits >> 28) & 1) != 0)
94    }
95    #[doc = "Bit 29 - Set 1 to enable SYSTEMTIMER clock"]
96    #[inline(always)]
97    pub fn systimer_clk_en(&self) -> SYSTIMER_CLK_EN_R {
98        SYSTIMER_CLK_EN_R::new(((self.bits >> 29) & 1) != 0)
99    }
100    #[doc = "Bit 30 - Set 1 to enable ADC2_ARB clock"]
101    #[inline(always)]
102    pub fn adc2_arb_clk_en(&self) -> ADC2_ARB_CLK_EN_R {
103        ADC2_ARB_CLK_EN_R::new(((self.bits >> 30) & 1) != 0)
104    }
105}
106#[cfg(feature = "impl-register-debug")]
107impl core::fmt::Debug for R {
108    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
109        f.debug_struct("PERIP_CLK_EN0")
110            .field("spi01_clk_en", &self.spi01_clk_en())
111            .field("uart_clk_en", &self.uart_clk_en())
112            .field("uart1_clk_en", &self.uart1_clk_en())
113            .field("spi2_clk_en", &self.spi2_clk_en())
114            .field("i2c_ext0_clk_en", &self.i2c_ext0_clk_en())
115            .field("ledc_clk_en", &self.ledc_clk_en())
116            .field("timergroup_clk_en", &self.timergroup_clk_en())
117            .field("uart_mem_clk_en", &self.uart_mem_clk_en())
118            .field("apb_saradc_clk_en", &self.apb_saradc_clk_en())
119            .field("systimer_clk_en", &self.systimer_clk_en())
120            .field("adc2_arb_clk_en", &self.adc2_arb_clk_en())
121            .finish()
122    }
123}
124impl W {
125    #[doc = "Bit 1 - Set 1 to enable SPI01 clock"]
126    #[inline(always)]
127    pub fn spi01_clk_en(&mut self) -> SPI01_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
128        SPI01_CLK_EN_W::new(self, 1)
129    }
130    #[doc = "Bit 2 - Set 1 to enable UART clock"]
131    #[inline(always)]
132    pub fn uart_clk_en(&mut self) -> UART_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
133        UART_CLK_EN_W::new(self, 2)
134    }
135    #[doc = "Bit 5 - Set 1 to enable UART1 clock"]
136    #[inline(always)]
137    pub fn uart1_clk_en(&mut self) -> UART1_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
138        UART1_CLK_EN_W::new(self, 5)
139    }
140    #[doc = "Bit 6 - Set 1 to enable SPI2 clock"]
141    #[inline(always)]
142    pub fn spi2_clk_en(&mut self) -> SPI2_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
143        SPI2_CLK_EN_W::new(self, 6)
144    }
145    #[doc = "Bit 7 - Set 1 to enable I2C_EXT0 clock"]
146    #[inline(always)]
147    pub fn i2c_ext0_clk_en(&mut self) -> I2C_EXT0_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
148        I2C_EXT0_CLK_EN_W::new(self, 7)
149    }
150    #[doc = "Bit 11 - Set 1 to enable LEDC clock"]
151    #[inline(always)]
152    pub fn ledc_clk_en(&mut self) -> LEDC_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
153        LEDC_CLK_EN_W::new(self, 11)
154    }
155    #[doc = "Bit 13 - Set 1 to enable TIMERGROUP clock"]
156    #[inline(always)]
157    pub fn timergroup_clk_en(&mut self) -> TIMERGROUP_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
158        TIMERGROUP_CLK_EN_W::new(self, 13)
159    }
160    #[doc = "Bit 24 - Set 1 to enable UART_MEM clock"]
161    #[inline(always)]
162    pub fn uart_mem_clk_en(&mut self) -> UART_MEM_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
163        UART_MEM_CLK_EN_W::new(self, 24)
164    }
165    #[doc = "Bit 28 - Set 1 to enable APB_SARADC clock"]
166    #[inline(always)]
167    pub fn apb_saradc_clk_en(&mut self) -> APB_SARADC_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
168        APB_SARADC_CLK_EN_W::new(self, 28)
169    }
170    #[doc = "Bit 29 - Set 1 to enable SYSTEMTIMER clock"]
171    #[inline(always)]
172    pub fn systimer_clk_en(&mut self) -> SYSTIMER_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
173        SYSTIMER_CLK_EN_W::new(self, 29)
174    }
175    #[doc = "Bit 30 - Set 1 to enable ADC2_ARB clock"]
176    #[inline(always)]
177    pub fn adc2_arb_clk_en(&mut self) -> ADC2_ARB_CLK_EN_W<PERIP_CLK_EN0_SPEC> {
178        ADC2_ARB_CLK_EN_W::new(self, 30)
179    }
180}
181#[doc = "peripheral clock gating register\n\nYou can [`read`](crate::Reg::read) this register and get [`perip_clk_en0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perip_clk_en0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
182pub struct PERIP_CLK_EN0_SPEC;
183impl crate::RegisterSpec for PERIP_CLK_EN0_SPEC {
184    type Ux = u32;
185}
186#[doc = "`read()` method returns [`perip_clk_en0::R`](R) reader structure"]
187impl crate::Readable for PERIP_CLK_EN0_SPEC {}
188#[doc = "`write(|w| ..)` method takes [`perip_clk_en0::W`](W) writer structure"]
189impl crate::Writable for PERIP_CLK_EN0_SPEC {
190    type Safety = crate::Unsafe;
191    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
192    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
193}
194#[doc = "`reset()` method sets PERIP_CLK_EN0 to value 0x7100_2066"]
195impl crate::Resettable for PERIP_CLK_EN0_SPEC {
196    const RESET_VALUE: u32 = 0x7100_2066;
197}
esp32c2/system/perip_clk_en0.rs

esp32c2/system/
perip_clk_en0.rs
