esp32c2/spi2/
dma_int_st.rs1#[doc = "Register `DMA_INT_ST` reader"]
2pub type R = crate::R<DMA_INT_ST_SPEC>;
3#[doc = "Field `DMA_INFIFO_FULL_ERR` reader - The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt."]
4pub type DMA_INFIFO_FULL_ERR_R = crate::BitReader;
5#[doc = "Field `DMA_OUTFIFO_EMPTY_ERR` reader - The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt."]
6pub type DMA_OUTFIFO_EMPTY_ERR_R = crate::BitReader;
7#[doc = "Field `SLV_EX_QPI` reader - The status bit for SPI slave Ex_QPI interrupt."]
8pub type SLV_EX_QPI_R = crate::BitReader;
9#[doc = "Field `SLV_EN_QPI` reader - The status bit for SPI slave En_QPI interrupt."]
10pub type SLV_EN_QPI_R = crate::BitReader;
11#[doc = "Field `SLV_CMD7` reader - The status bit for SPI slave CMD7 interrupt."]
12pub type SLV_CMD7_R = crate::BitReader;
13#[doc = "Field `SLV_CMD8` reader - The status bit for SPI slave CMD8 interrupt."]
14pub type SLV_CMD8_R = crate::BitReader;
15#[doc = "Field `SLV_CMD9` reader - The status bit for SPI slave CMD9 interrupt."]
16pub type SLV_CMD9_R = crate::BitReader;
17#[doc = "Field `SLV_CMDA` reader - The status bit for SPI slave CMDA interrupt."]
18pub type SLV_CMDA_R = crate::BitReader;
19#[doc = "Field `SLV_RD_DMA_DONE` reader - The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt."]
20pub type SLV_RD_DMA_DONE_R = crate::BitReader;
21#[doc = "Field `SLV_WR_DMA_DONE` reader - The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt."]
22pub type SLV_WR_DMA_DONE_R = crate::BitReader;
23#[doc = "Field `SLV_RD_BUF_DONE` reader - The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt."]
24pub type SLV_RD_BUF_DONE_R = crate::BitReader;
25#[doc = "Field `SLV_WR_BUF_DONE` reader - The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt."]
26pub type SLV_WR_BUF_DONE_R = crate::BitReader;
27#[doc = "Field `TRANS_DONE` reader - The status bit for SPI_TRANS_DONE_INT interrupt."]
28pub type TRANS_DONE_R = crate::BitReader;
29#[doc = "Field `DMA_SEG_TRANS_DONE` reader - The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt."]
30pub type DMA_SEG_TRANS_DONE_R = crate::BitReader;
31#[doc = "Field `SEG_MAGIC_ERR` reader - The status bit for SPI_SEG_MAGIC_ERR_INT interrupt."]
32pub type SEG_MAGIC_ERR_R = crate::BitReader;
33#[doc = "Field `SLV_BUF_ADDR_ERR` reader - The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt."]
34pub type SLV_BUF_ADDR_ERR_R = crate::BitReader;
35#[doc = "Field `SLV_CMD_ERR` reader - The status bit for SPI_SLV_CMD_ERR_INT interrupt."]
36pub type SLV_CMD_ERR_R = crate::BitReader;
37#[doc = "Field `MST_RX_AFIFO_WFULL_ERR` reader - The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt."]
38pub type MST_RX_AFIFO_WFULL_ERR_R = crate::BitReader;
39#[doc = "Field `MST_TX_AFIFO_REMPTY_ERR` reader - The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt."]
40pub type MST_TX_AFIFO_REMPTY_ERR_R = crate::BitReader;
41#[doc = "Field `APP2` reader - The status bit for SPI_APP2_INT interrupt."]
42pub type APP2_R = crate::BitReader;
43#[doc = "Field `APP1` reader - The status bit for SPI_APP1_INT interrupt."]
44pub type APP1_R = crate::BitReader;
45impl R {
46 #[doc = "Bit 0 - The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt."]
47 #[inline(always)]
48 pub fn dma_infifo_full_err(&self) -> DMA_INFIFO_FULL_ERR_R {
49 DMA_INFIFO_FULL_ERR_R::new((self.bits & 1) != 0)
50 }
51 #[doc = "Bit 1 - The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt."]
52 #[inline(always)]
53 pub fn dma_outfifo_empty_err(&self) -> DMA_OUTFIFO_EMPTY_ERR_R {
54 DMA_OUTFIFO_EMPTY_ERR_R::new(((self.bits >> 1) & 1) != 0)
55 }
56 #[doc = "Bit 2 - The status bit for SPI slave Ex_QPI interrupt."]
57 #[inline(always)]
58 pub fn slv_ex_qpi(&self) -> SLV_EX_QPI_R {
59 SLV_EX_QPI_R::new(((self.bits >> 2) & 1) != 0)
60 }
61 #[doc = "Bit 3 - The status bit for SPI slave En_QPI interrupt."]
62 #[inline(always)]
63 pub fn slv_en_qpi(&self) -> SLV_EN_QPI_R {
64 SLV_EN_QPI_R::new(((self.bits >> 3) & 1) != 0)
65 }
66 #[doc = "Bit 4 - The status bit for SPI slave CMD7 interrupt."]
67 #[inline(always)]
68 pub fn slv_cmd7(&self) -> SLV_CMD7_R {
69 SLV_CMD7_R::new(((self.bits >> 4) & 1) != 0)
70 }
71 #[doc = "Bit 5 - The status bit for SPI slave CMD8 interrupt."]
72 #[inline(always)]
73 pub fn slv_cmd8(&self) -> SLV_CMD8_R {
74 SLV_CMD8_R::new(((self.bits >> 5) & 1) != 0)
75 }
76 #[doc = "Bit 6 - The status bit for SPI slave CMD9 interrupt."]
77 #[inline(always)]
78 pub fn slv_cmd9(&self) -> SLV_CMD9_R {
79 SLV_CMD9_R::new(((self.bits >> 6) & 1) != 0)
80 }
81 #[doc = "Bit 7 - The status bit for SPI slave CMDA interrupt."]
82 #[inline(always)]
83 pub fn slv_cmda(&self) -> SLV_CMDA_R {
84 SLV_CMDA_R::new(((self.bits >> 7) & 1) != 0)
85 }
86 #[doc = "Bit 8 - The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt."]
87 #[inline(always)]
88 pub fn slv_rd_dma_done(&self) -> SLV_RD_DMA_DONE_R {
89 SLV_RD_DMA_DONE_R::new(((self.bits >> 8) & 1) != 0)
90 }
91 #[doc = "Bit 9 - The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt."]
92 #[inline(always)]
93 pub fn slv_wr_dma_done(&self) -> SLV_WR_DMA_DONE_R {
94 SLV_WR_DMA_DONE_R::new(((self.bits >> 9) & 1) != 0)
95 }
96 #[doc = "Bit 10 - The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt."]
97 #[inline(always)]
98 pub fn slv_rd_buf_done(&self) -> SLV_RD_BUF_DONE_R {
99 SLV_RD_BUF_DONE_R::new(((self.bits >> 10) & 1) != 0)
100 }
101 #[doc = "Bit 11 - The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt."]
102 #[inline(always)]
103 pub fn slv_wr_buf_done(&self) -> SLV_WR_BUF_DONE_R {
104 SLV_WR_BUF_DONE_R::new(((self.bits >> 11) & 1) != 0)
105 }
106 #[doc = "Bit 12 - The status bit for SPI_TRANS_DONE_INT interrupt."]
107 #[inline(always)]
108 pub fn trans_done(&self) -> TRANS_DONE_R {
109 TRANS_DONE_R::new(((self.bits >> 12) & 1) != 0)
110 }
111 #[doc = "Bit 13 - The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt."]
112 #[inline(always)]
113 pub fn dma_seg_trans_done(&self) -> DMA_SEG_TRANS_DONE_R {
114 DMA_SEG_TRANS_DONE_R::new(((self.bits >> 13) & 1) != 0)
115 }
116 #[doc = "Bit 14 - The status bit for SPI_SEG_MAGIC_ERR_INT interrupt."]
117 #[inline(always)]
118 pub fn seg_magic_err(&self) -> SEG_MAGIC_ERR_R {
119 SEG_MAGIC_ERR_R::new(((self.bits >> 14) & 1) != 0)
120 }
121 #[doc = "Bit 15 - The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt."]
122 #[inline(always)]
123 pub fn slv_buf_addr_err(&self) -> SLV_BUF_ADDR_ERR_R {
124 SLV_BUF_ADDR_ERR_R::new(((self.bits >> 15) & 1) != 0)
125 }
126 #[doc = "Bit 16 - The status bit for SPI_SLV_CMD_ERR_INT interrupt."]
127 #[inline(always)]
128 pub fn slv_cmd_err(&self) -> SLV_CMD_ERR_R {
129 SLV_CMD_ERR_R::new(((self.bits >> 16) & 1) != 0)
130 }
131 #[doc = "Bit 17 - The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt."]
132 #[inline(always)]
133 pub fn mst_rx_afifo_wfull_err(&self) -> MST_RX_AFIFO_WFULL_ERR_R {
134 MST_RX_AFIFO_WFULL_ERR_R::new(((self.bits >> 17) & 1) != 0)
135 }
136 #[doc = "Bit 18 - The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt."]
137 #[inline(always)]
138 pub fn mst_tx_afifo_rempty_err(&self) -> MST_TX_AFIFO_REMPTY_ERR_R {
139 MST_TX_AFIFO_REMPTY_ERR_R::new(((self.bits >> 18) & 1) != 0)
140 }
141 #[doc = "Bit 19 - The status bit for SPI_APP2_INT interrupt."]
142 #[inline(always)]
143 pub fn app2(&self) -> APP2_R {
144 APP2_R::new(((self.bits >> 19) & 1) != 0)
145 }
146 #[doc = "Bit 20 - The status bit for SPI_APP1_INT interrupt."]
147 #[inline(always)]
148 pub fn app1(&self) -> APP1_R {
149 APP1_R::new(((self.bits >> 20) & 1) != 0)
150 }
151}
152#[cfg(feature = "impl-register-debug")]
153impl core::fmt::Debug for R {
154 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
155 f.debug_struct("DMA_INT_ST")
156 .field("dma_infifo_full_err", &self.dma_infifo_full_err())
157 .field("dma_outfifo_empty_err", &self.dma_outfifo_empty_err())
158 .field("slv_ex_qpi", &self.slv_ex_qpi())
159 .field("slv_en_qpi", &self.slv_en_qpi())
160 .field("slv_cmd7", &self.slv_cmd7())
161 .field("slv_cmd8", &self.slv_cmd8())
162 .field("slv_cmd9", &self.slv_cmd9())
163 .field("slv_cmda", &self.slv_cmda())
164 .field("slv_rd_dma_done", &self.slv_rd_dma_done())
165 .field("slv_wr_dma_done", &self.slv_wr_dma_done())
166 .field("slv_rd_buf_done", &self.slv_rd_buf_done())
167 .field("slv_wr_buf_done", &self.slv_wr_buf_done())
168 .field("trans_done", &self.trans_done())
169 .field("dma_seg_trans_done", &self.dma_seg_trans_done())
170 .field("seg_magic_err", &self.seg_magic_err())
171 .field("slv_buf_addr_err", &self.slv_buf_addr_err())
172 .field("slv_cmd_err", &self.slv_cmd_err())
173 .field("mst_rx_afifo_wfull_err", &self.mst_rx_afifo_wfull_err())
174 .field("mst_tx_afifo_rempty_err", &self.mst_tx_afifo_rempty_err())
175 .field("app2", &self.app2())
176 .field("app1", &self.app1())
177 .finish()
178 }
179}
180#[doc = "SPI interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
181pub struct DMA_INT_ST_SPEC;
182impl crate::RegisterSpec for DMA_INT_ST_SPEC {
183 type Ux = u32;
184}
185#[doc = "`read()` method returns [`dma_int_st::R`](R) reader structure"]
186impl crate::Readable for DMA_INT_ST_SPEC {}
187#[doc = "`reset()` method sets DMA_INT_ST to value 0"]
188impl crate::Resettable for DMA_INT_ST_SPEC {
189 const RESET_VALUE: u32 = 0;
190}