esp32c2/spi0/
din_mode.rs

1#[doc = "Register `DIN_MODE` reader"]
2pub type R = crate::R<DIN_MODE_SPEC>;
3#[doc = "Field `DIN0_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
4pub type DIN0_MODE_R = crate::FieldReader;
5#[doc = "Field `DIN1_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
6pub type DIN1_MODE_R = crate::FieldReader;
7#[doc = "Field `DIN2_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
8pub type DIN2_MODE_R = crate::FieldReader;
9#[doc = "Field `DIN3_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
10pub type DIN3_MODE_R = crate::FieldReader;
11impl R {
12    #[doc = "Bits 0:1 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
13    #[inline(always)]
14    pub fn din0_mode(&self) -> DIN0_MODE_R {
15        DIN0_MODE_R::new((self.bits & 3) as u8)
16    }
17    #[doc = "Bits 2:3 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
18    #[inline(always)]
19    pub fn din1_mode(&self) -> DIN1_MODE_R {
20        DIN1_MODE_R::new(((self.bits >> 2) & 3) as u8)
21    }
22    #[doc = "Bits 4:5 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
23    #[inline(always)]
24    pub fn din2_mode(&self) -> DIN2_MODE_R {
25        DIN2_MODE_R::new(((self.bits >> 4) & 3) as u8)
26    }
27    #[doc = "Bits 6:7 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
28    #[inline(always)]
29    pub fn din3_mode(&self) -> DIN3_MODE_R {
30        DIN3_MODE_R::new(((self.bits >> 6) & 3) as u8)
31    }
32}
33#[cfg(feature = "impl-register-debug")]
34impl core::fmt::Debug for R {
35    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
36        f.debug_struct("DIN_MODE")
37            .field("din0_mode", &self.din0_mode())
38            .field("din1_mode", &self.din1_mode())
39            .field("din2_mode", &self.din2_mode())
40            .field("din3_mode", &self.din3_mode())
41            .finish()
42    }
43}
44#[doc = "SPI0 input delay mode control register\n\nYou can [`read`](crate::Reg::read) this register and get [`din_mode::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
45pub struct DIN_MODE_SPEC;
46impl crate::RegisterSpec for DIN_MODE_SPEC {
47    type Ux = u32;
48}
49#[doc = "`read()` method returns [`din_mode::R`](R) reader structure"]
50impl crate::Readable for DIN_MODE_SPEC {}
51#[doc = "`reset()` method sets DIN_MODE to value 0"]
52impl crate::Resettable for DIN_MODE_SPEC {
53    const RESET_VALUE: u32 = 0;
54}
esp32c2/spi0/din_mode.rs

esp32c2/spi0/
din_mode.rs
