1#[doc = "Register `INT_ENA` reader"]
2pub type R = crate::R<INT_ENA_SPEC>;
3#[doc = "Register `INT_ENA` writer"]
4pub type W = crate::W<INT_ENA_SPEC>;
5#[doc = "Field `TIMER_OVF(0-3)` reader - The interrupt enable bit for the TIMER%s_OVF interrupt."]
6pub type TIMER_OVF_R = crate::BitReader;
7#[doc = "Field `TIMER_OVF(0-3)` writer - The interrupt enable bit for the TIMER%s_OVF interrupt."]
8pub type TIMER_OVF_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `DUTY_CHNG_END_CH(0-5)` reader - The interrupt enable bit for the DUTY_CHNG_END_CH%s interrupt."]
10pub type DUTY_CHNG_END_CH_R = crate::BitReader;
11#[doc = "Field `DUTY_CHNG_END_CH(0-5)` writer - The interrupt enable bit for the DUTY_CHNG_END_CH%s interrupt."]
12pub type DUTY_CHNG_END_CH_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `OVF_CNT_CH(0-5)` reader - The interrupt enable bit for the OVF_CNT_CH%s interrupt."]
14pub type OVF_CNT_CH_R = crate::BitReader;
15#[doc = "Field `OVF_CNT_CH(0-5)` writer - The interrupt enable bit for the OVF_CNT_CH%s interrupt."]
16pub type OVF_CNT_CH_W<'a, REG> = crate::BitWriter<'a, REG>;
17impl R {
18 #[doc = "The interrupt enable bit for the TIMER(0-3)_OVF interrupt."]
19 #[doc = ""]
20 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_OVF` field.</div>"]
21 #[inline(always)]
22 pub fn timer_ovf(&self, n: u8) -> TIMER_OVF_R {
23 #[allow(clippy::no_effect)]
24 [(); 4][n as usize];
25 TIMER_OVF_R::new(((self.bits >> n) & 1) != 0)
26 }
27 #[doc = "Iterator for array of:"]
28 #[doc = "The interrupt enable bit for the TIMER(0-3)_OVF interrupt."]
29 #[inline(always)]
30 pub fn timer_ovf_iter(&self) -> impl Iterator<Item = TIMER_OVF_R> + '_ {
31 (0..4).map(move |n| TIMER_OVF_R::new(((self.bits >> n) & 1) != 0))
32 }
33 #[doc = "Bit 0 - The interrupt enable bit for the TIMER0_OVF interrupt."]
34 #[inline(always)]
35 pub fn timer0_ovf(&self) -> TIMER_OVF_R {
36 TIMER_OVF_R::new((self.bits & 1) != 0)
37 }
38 #[doc = "Bit 1 - The interrupt enable bit for the TIMER1_OVF interrupt."]
39 #[inline(always)]
40 pub fn timer1_ovf(&self) -> TIMER_OVF_R {
41 TIMER_OVF_R::new(((self.bits >> 1) & 1) != 0)
42 }
43 #[doc = "Bit 2 - The interrupt enable bit for the TIMER2_OVF interrupt."]
44 #[inline(always)]
45 pub fn timer2_ovf(&self) -> TIMER_OVF_R {
46 TIMER_OVF_R::new(((self.bits >> 2) & 1) != 0)
47 }
48 #[doc = "Bit 3 - The interrupt enable bit for the TIMER3_OVF interrupt."]
49 #[inline(always)]
50 pub fn timer3_ovf(&self) -> TIMER_OVF_R {
51 TIMER_OVF_R::new(((self.bits >> 3) & 1) != 0)
52 }
53 #[doc = "The interrupt enable bit for the DUTY_CHNG_END_CH(0-5) interrupt."]
54 #[doc = ""]
55 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `DUTY_CHNG_END_CH0` field.</div>"]
56 #[inline(always)]
57 pub fn duty_chng_end_ch(&self, n: u8) -> DUTY_CHNG_END_CH_R {
58 #[allow(clippy::no_effect)]
59 [(); 6][n as usize];
60 DUTY_CHNG_END_CH_R::new(((self.bits >> (n + 4)) & 1) != 0)
61 }
62 #[doc = "Iterator for array of:"]
63 #[doc = "The interrupt enable bit for the DUTY_CHNG_END_CH(0-5) interrupt."]
64 #[inline(always)]
65 pub fn duty_chng_end_ch_iter(&self) -> impl Iterator<Item = DUTY_CHNG_END_CH_R> + '_ {
66 (0..6).map(move |n| DUTY_CHNG_END_CH_R::new(((self.bits >> (n + 4)) & 1) != 0))
67 }
68 #[doc = "Bit 4 - The interrupt enable bit for the DUTY_CHNG_END_CH0 interrupt."]
69 #[inline(always)]
70 pub fn duty_chng_end_ch0(&self) -> DUTY_CHNG_END_CH_R {
71 DUTY_CHNG_END_CH_R::new(((self.bits >> 4) & 1) != 0)
72 }
73 #[doc = "Bit 5 - The interrupt enable bit for the DUTY_CHNG_END_CH1 interrupt."]
74 #[inline(always)]
75 pub fn duty_chng_end_ch1(&self) -> DUTY_CHNG_END_CH_R {
76 DUTY_CHNG_END_CH_R::new(((self.bits >> 5) & 1) != 0)
77 }
78 #[doc = "Bit 6 - The interrupt enable bit for the DUTY_CHNG_END_CH2 interrupt."]
79 #[inline(always)]
80 pub fn duty_chng_end_ch2(&self) -> DUTY_CHNG_END_CH_R {
81 DUTY_CHNG_END_CH_R::new(((self.bits >> 6) & 1) != 0)
82 }
83 #[doc = "Bit 7 - The interrupt enable bit for the DUTY_CHNG_END_CH3 interrupt."]
84 #[inline(always)]
85 pub fn duty_chng_end_ch3(&self) -> DUTY_CHNG_END_CH_R {
86 DUTY_CHNG_END_CH_R::new(((self.bits >> 7) & 1) != 0)
87 }
88 #[doc = "Bit 8 - The interrupt enable bit for the DUTY_CHNG_END_CH4 interrupt."]
89 #[inline(always)]
90 pub fn duty_chng_end_ch4(&self) -> DUTY_CHNG_END_CH_R {
91 DUTY_CHNG_END_CH_R::new(((self.bits >> 8) & 1) != 0)
92 }
93 #[doc = "Bit 9 - The interrupt enable bit for the DUTY_CHNG_END_CH5 interrupt."]
94 #[inline(always)]
95 pub fn duty_chng_end_ch5(&self) -> DUTY_CHNG_END_CH_R {
96 DUTY_CHNG_END_CH_R::new(((self.bits >> 9) & 1) != 0)
97 }
98 #[doc = "The interrupt enable bit for the OVF_CNT_CH(0-5) interrupt."]
99 #[doc = ""]
100 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `OVF_CNT_CH0` field.</div>"]
101 #[inline(always)]
102 pub fn ovf_cnt_ch(&self, n: u8) -> OVF_CNT_CH_R {
103 #[allow(clippy::no_effect)]
104 [(); 6][n as usize];
105 OVF_CNT_CH_R::new(((self.bits >> (n + 10)) & 1) != 0)
106 }
107 #[doc = "Iterator for array of:"]
108 #[doc = "The interrupt enable bit for the OVF_CNT_CH(0-5) interrupt."]
109 #[inline(always)]
110 pub fn ovf_cnt_ch_iter(&self) -> impl Iterator<Item = OVF_CNT_CH_R> + '_ {
111 (0..6).map(move |n| OVF_CNT_CH_R::new(((self.bits >> (n + 10)) & 1) != 0))
112 }
113 #[doc = "Bit 10 - The interrupt enable bit for the OVF_CNT_CH0 interrupt."]
114 #[inline(always)]
115 pub fn ovf_cnt_ch0(&self) -> OVF_CNT_CH_R {
116 OVF_CNT_CH_R::new(((self.bits >> 10) & 1) != 0)
117 }
118 #[doc = "Bit 11 - The interrupt enable bit for the OVF_CNT_CH1 interrupt."]
119 #[inline(always)]
120 pub fn ovf_cnt_ch1(&self) -> OVF_CNT_CH_R {
121 OVF_CNT_CH_R::new(((self.bits >> 11) & 1) != 0)
122 }
123 #[doc = "Bit 12 - The interrupt enable bit for the OVF_CNT_CH2 interrupt."]
124 #[inline(always)]
125 pub fn ovf_cnt_ch2(&self) -> OVF_CNT_CH_R {
126 OVF_CNT_CH_R::new(((self.bits >> 12) & 1) != 0)
127 }
128 #[doc = "Bit 13 - The interrupt enable bit for the OVF_CNT_CH3 interrupt."]
129 #[inline(always)]
130 pub fn ovf_cnt_ch3(&self) -> OVF_CNT_CH_R {
131 OVF_CNT_CH_R::new(((self.bits >> 13) & 1) != 0)
132 }
133 #[doc = "Bit 14 - The interrupt enable bit for the OVF_CNT_CH4 interrupt."]
134 #[inline(always)]
135 pub fn ovf_cnt_ch4(&self) -> OVF_CNT_CH_R {
136 OVF_CNT_CH_R::new(((self.bits >> 14) & 1) != 0)
137 }
138 #[doc = "Bit 15 - The interrupt enable bit for the OVF_CNT_CH5 interrupt."]
139 #[inline(always)]
140 pub fn ovf_cnt_ch5(&self) -> OVF_CNT_CH_R {
141 OVF_CNT_CH_R::new(((self.bits >> 15) & 1) != 0)
142 }
143}
144#[cfg(feature = "impl-register-debug")]
145impl core::fmt::Debug for R {
146 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
147 f.debug_struct("INT_ENA")
148 .field("timer0_ovf", &self.timer0_ovf())
149 .field("timer1_ovf", &self.timer1_ovf())
150 .field("timer2_ovf", &self.timer2_ovf())
151 .field("timer3_ovf", &self.timer3_ovf())
152 .field("duty_chng_end_ch0", &self.duty_chng_end_ch0())
153 .field("duty_chng_end_ch1", &self.duty_chng_end_ch1())
154 .field("duty_chng_end_ch2", &self.duty_chng_end_ch2())
155 .field("duty_chng_end_ch3", &self.duty_chng_end_ch3())
156 .field("duty_chng_end_ch4", &self.duty_chng_end_ch4())
157 .field("duty_chng_end_ch5", &self.duty_chng_end_ch5())
158 .field("ovf_cnt_ch0", &self.ovf_cnt_ch0())
159 .field("ovf_cnt_ch1", &self.ovf_cnt_ch1())
160 .field("ovf_cnt_ch2", &self.ovf_cnt_ch2())
161 .field("ovf_cnt_ch3", &self.ovf_cnt_ch3())
162 .field("ovf_cnt_ch4", &self.ovf_cnt_ch4())
163 .field("ovf_cnt_ch5", &self.ovf_cnt_ch5())
164 .finish()
165 }
166}
167impl W {
168 #[doc = "The interrupt enable bit for the TIMER(0-3)_OVF interrupt."]
169 #[doc = ""]
170 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_OVF` field.</div>"]
171 #[inline(always)]
172 pub fn timer_ovf(&mut self, n: u8) -> TIMER_OVF_W<INT_ENA_SPEC> {
173 #[allow(clippy::no_effect)]
174 [(); 4][n as usize];
175 TIMER_OVF_W::new(self, n)
176 }
177 #[doc = "Bit 0 - The interrupt enable bit for the TIMER0_OVF interrupt."]
178 #[inline(always)]
179 pub fn timer0_ovf(&mut self) -> TIMER_OVF_W<INT_ENA_SPEC> {
180 TIMER_OVF_W::new(self, 0)
181 }
182 #[doc = "Bit 1 - The interrupt enable bit for the TIMER1_OVF interrupt."]
183 #[inline(always)]
184 pub fn timer1_ovf(&mut self) -> TIMER_OVF_W<INT_ENA_SPEC> {
185 TIMER_OVF_W::new(self, 1)
186 }
187 #[doc = "Bit 2 - The interrupt enable bit for the TIMER2_OVF interrupt."]
188 #[inline(always)]
189 pub fn timer2_ovf(&mut self) -> TIMER_OVF_W<INT_ENA_SPEC> {
190 TIMER_OVF_W::new(self, 2)
191 }
192 #[doc = "Bit 3 - The interrupt enable bit for the TIMER3_OVF interrupt."]
193 #[inline(always)]
194 pub fn timer3_ovf(&mut self) -> TIMER_OVF_W<INT_ENA_SPEC> {
195 TIMER_OVF_W::new(self, 3)
196 }
197 #[doc = "The interrupt enable bit for the DUTY_CHNG_END_CH(0-5) interrupt."]
198 #[doc = ""]
199 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `DUTY_CHNG_END_CH0` field.</div>"]
200 #[inline(always)]
201 pub fn duty_chng_end_ch(&mut self, n: u8) -> DUTY_CHNG_END_CH_W<INT_ENA_SPEC> {
202 #[allow(clippy::no_effect)]
203 [(); 6][n as usize];
204 DUTY_CHNG_END_CH_W::new(self, n + 4)
205 }
206 #[doc = "Bit 4 - The interrupt enable bit for the DUTY_CHNG_END_CH0 interrupt."]
207 #[inline(always)]
208 pub fn duty_chng_end_ch0(&mut self) -> DUTY_CHNG_END_CH_W<INT_ENA_SPEC> {
209 DUTY_CHNG_END_CH_W::new(self, 4)
210 }
211 #[doc = "Bit 5 - The interrupt enable bit for the DUTY_CHNG_END_CH1 interrupt."]
212 #[inline(always)]
213 pub fn duty_chng_end_ch1(&mut self) -> DUTY_CHNG_END_CH_W<INT_ENA_SPEC> {
214 DUTY_CHNG_END_CH_W::new(self, 5)
215 }
216 #[doc = "Bit 6 - The interrupt enable bit for the DUTY_CHNG_END_CH2 interrupt."]
217 #[inline(always)]
218 pub fn duty_chng_end_ch2(&mut self) -> DUTY_CHNG_END_CH_W<INT_ENA_SPEC> {
219 DUTY_CHNG_END_CH_W::new(self, 6)
220 }
221 #[doc = "Bit 7 - The interrupt enable bit for the DUTY_CHNG_END_CH3 interrupt."]
222 #[inline(always)]
223 pub fn duty_chng_end_ch3(&mut self) -> DUTY_CHNG_END_CH_W<INT_ENA_SPEC> {
224 DUTY_CHNG_END_CH_W::new(self, 7)
225 }
226 #[doc = "Bit 8 - The interrupt enable bit for the DUTY_CHNG_END_CH4 interrupt."]
227 #[inline(always)]
228 pub fn duty_chng_end_ch4(&mut self) -> DUTY_CHNG_END_CH_W<INT_ENA_SPEC> {
229 DUTY_CHNG_END_CH_W::new(self, 8)
230 }
231 #[doc = "Bit 9 - The interrupt enable bit for the DUTY_CHNG_END_CH5 interrupt."]
232 #[inline(always)]
233 pub fn duty_chng_end_ch5(&mut self) -> DUTY_CHNG_END_CH_W<INT_ENA_SPEC> {
234 DUTY_CHNG_END_CH_W::new(self, 9)
235 }
236 #[doc = "The interrupt enable bit for the OVF_CNT_CH(0-5) interrupt."]
237 #[doc = ""]
238 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `OVF_CNT_CH0` field.</div>"]
239 #[inline(always)]
240 pub fn ovf_cnt_ch(&mut self, n: u8) -> OVF_CNT_CH_W<INT_ENA_SPEC> {
241 #[allow(clippy::no_effect)]
242 [(); 6][n as usize];
243 OVF_CNT_CH_W::new(self, n + 10)
244 }
245 #[doc = "Bit 10 - The interrupt enable bit for the OVF_CNT_CH0 interrupt."]
246 #[inline(always)]
247 pub fn ovf_cnt_ch0(&mut self) -> OVF_CNT_CH_W<INT_ENA_SPEC> {
248 OVF_CNT_CH_W::new(self, 10)
249 }
250 #[doc = "Bit 11 - The interrupt enable bit for the OVF_CNT_CH1 interrupt."]
251 #[inline(always)]
252 pub fn ovf_cnt_ch1(&mut self) -> OVF_CNT_CH_W<INT_ENA_SPEC> {
253 OVF_CNT_CH_W::new(self, 11)
254 }
255 #[doc = "Bit 12 - The interrupt enable bit for the OVF_CNT_CH2 interrupt."]
256 #[inline(always)]
257 pub fn ovf_cnt_ch2(&mut self) -> OVF_CNT_CH_W<INT_ENA_SPEC> {
258 OVF_CNT_CH_W::new(self, 12)
259 }
260 #[doc = "Bit 13 - The interrupt enable bit for the OVF_CNT_CH3 interrupt."]
261 #[inline(always)]
262 pub fn ovf_cnt_ch3(&mut self) -> OVF_CNT_CH_W<INT_ENA_SPEC> {
263 OVF_CNT_CH_W::new(self, 13)
264 }
265 #[doc = "Bit 14 - The interrupt enable bit for the OVF_CNT_CH4 interrupt."]
266 #[inline(always)]
267 pub fn ovf_cnt_ch4(&mut self) -> OVF_CNT_CH_W<INT_ENA_SPEC> {
268 OVF_CNT_CH_W::new(self, 14)
269 }
270 #[doc = "Bit 15 - The interrupt enable bit for the OVF_CNT_CH5 interrupt."]
271 #[inline(always)]
272 pub fn ovf_cnt_ch5(&mut self) -> OVF_CNT_CH_W<INT_ENA_SPEC> {
273 OVF_CNT_CH_W::new(self, 15)
274 }
275}
276#[doc = "Interrupt enable bits\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
277pub struct INT_ENA_SPEC;
278impl crate::RegisterSpec for INT_ENA_SPEC {
279 type Ux = u32;
280}
281#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"]
282impl crate::Readable for INT_ENA_SPEC {}
283#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"]
284impl crate::Writable for INT_ENA_SPEC {
285 type Safety = crate::Unsafe;
286 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
287 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
288}
289#[doc = "`reset()` method sets INT_ENA to value 0"]
290impl crate::Resettable for INT_ENA_SPEC {
291 const RESET_VALUE: u32 = 0;
292}