esp32c2/ledc/
conf.rs

1#[doc = "Register `CONF` reader"]
2pub type R = crate::R<CONF_SPEC>;
3#[doc = "Register `CONF` writer"]
4pub type W = crate::W<CONF_SPEC>;
5#[doc = "Field `APB_CLK_SEL` reader - This bit is used to select clock source for the 4 timers . 2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK"]
6pub type APB_CLK_SEL_R = crate::FieldReader;
7#[doc = "Field `APB_CLK_SEL` writer - This bit is used to select clock source for the 4 timers . 2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK"]
8pub type APB_CLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `CLK_EN` reader - This bit is used to control clock. 1'b1: Force clock on for register. 1'h0: Support clock only when application writes registers."]
10pub type CLK_EN_R = crate::BitReader;
11#[doc = "Field `CLK_EN` writer - This bit is used to control clock. 1'b1: Force clock on for register. 1'h0: Support clock only when application writes registers."]
12pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13impl R {
14    #[doc = "Bits 0:1 - This bit is used to select clock source for the 4 timers . 2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK"]
15    #[inline(always)]
16    pub fn apb_clk_sel(&self) -> APB_CLK_SEL_R {
17        APB_CLK_SEL_R::new((self.bits & 3) as u8)
18    }
19    #[doc = "Bit 31 - This bit is used to control clock. 1'b1: Force clock on for register. 1'h0: Support clock only when application writes registers."]
20    #[inline(always)]
21    pub fn clk_en(&self) -> CLK_EN_R {
22        CLK_EN_R::new(((self.bits >> 31) & 1) != 0)
23    }
24}
25#[cfg(feature = "impl-register-debug")]
26impl core::fmt::Debug for R {
27    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
28        f.debug_struct("CONF")
29            .field("apb_clk_sel", &self.apb_clk_sel())
30            .field("clk_en", &self.clk_en())
31            .finish()
32    }
33}
34impl W {
35    #[doc = "Bits 0:1 - This bit is used to select clock source for the 4 timers . 2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK"]
36    #[inline(always)]
37    pub fn apb_clk_sel(&mut self) -> APB_CLK_SEL_W<CONF_SPEC> {
38        APB_CLK_SEL_W::new(self, 0)
39    }
40    #[doc = "Bit 31 - This bit is used to control clock. 1'b1: Force clock on for register. 1'h0: Support clock only when application writes registers."]
41    #[inline(always)]
42    pub fn clk_en(&mut self) -> CLK_EN_W<CONF_SPEC> {
43        CLK_EN_W::new(self, 31)
44    }
45}
46#[doc = "Global ledc configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
47pub struct CONF_SPEC;
48impl crate::RegisterSpec for CONF_SPEC {
49    type Ux = u32;
50}
51#[doc = "`read()` method returns [`conf::R`](R) reader structure"]
52impl crate::Readable for CONF_SPEC {}
53#[doc = "`write(|w| ..)` method takes [`conf::W`](W) writer structure"]
54impl crate::Writable for CONF_SPEC {
55    type Safety = crate::Unsafe;
56    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
57    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
58}
59#[doc = "`reset()` method sets CONF to value 0"]
60impl crate::Resettable for CONF_SPEC {
61    const RESET_VALUE: u32 = 0;
62}
esp32c2/ledc/conf.rs

esp32c2/ledc/
conf.rs
