1#[doc = "Register `PIN%s` reader"]
2pub type R = crate::R<PIN_SPEC>;
3#[doc = "Register `PIN%s` writer"]
4pub type W = crate::W<PIN_SPEC>;
5#[doc = "Field `SYNC2_BYPASS` reader - set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge."]
6pub type SYNC2_BYPASS_R = crate::FieldReader;
7#[doc = "Field `SYNC2_BYPASS` writer - set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge."]
8pub type SYNC2_BYPASS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `PAD_DRIVER` reader - set this bit to select pad driver. 1:open-drain. 0:normal."]
10pub type PAD_DRIVER_R = crate::BitReader;
11#[doc = "Field `PAD_DRIVER` writer - set this bit to select pad driver. 1:open-drain. 0:normal."]
12pub type PAD_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `SYNC1_BYPASS` reader - set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge."]
14pub type SYNC1_BYPASS_R = crate::FieldReader;
15#[doc = "Field `SYNC1_BYPASS` writer - set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge."]
16pub type SYNC1_BYPASS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
17#[doc = "Field `INT_TYPE` reader - set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level"]
18pub type INT_TYPE_R = crate::FieldReader;
19#[doc = "Field `INT_TYPE` writer - set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level"]
20pub type INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
21#[doc = "Field `WAKEUP_ENABLE` reader - set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)"]
22pub type WAKEUP_ENABLE_R = crate::BitReader;
23#[doc = "Field `WAKEUP_ENABLE` writer - set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)"]
24pub type WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `CONFIG` reader - reserved"]
26pub type CONFIG_R = crate::FieldReader;
27#[doc = "Field `CONFIG` writer - reserved"]
28pub type CONFIG_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
29#[doc = "Field `INT_ENA` reader - set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt."]
30pub type INT_ENA_R = crate::FieldReader;
31#[doc = "Field `INT_ENA` writer - set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt."]
32pub type INT_ENA_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
33impl R {
34 #[doc = "Bits 0:1 - set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge."]
35 #[inline(always)]
36 pub fn sync2_bypass(&self) -> SYNC2_BYPASS_R {
37 SYNC2_BYPASS_R::new((self.bits & 3) as u8)
38 }
39 #[doc = "Bit 2 - set this bit to select pad driver. 1:open-drain. 0:normal."]
40 #[inline(always)]
41 pub fn pad_driver(&self) -> PAD_DRIVER_R {
42 PAD_DRIVER_R::new(((self.bits >> 2) & 1) != 0)
43 }
44 #[doc = "Bits 3:4 - set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge."]
45 #[inline(always)]
46 pub fn sync1_bypass(&self) -> SYNC1_BYPASS_R {
47 SYNC1_BYPASS_R::new(((self.bits >> 3) & 3) as u8)
48 }
49 #[doc = "Bits 7:9 - set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level"]
50 #[inline(always)]
51 pub fn int_type(&self) -> INT_TYPE_R {
52 INT_TYPE_R::new(((self.bits >> 7) & 7) as u8)
53 }
54 #[doc = "Bit 10 - set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)"]
55 #[inline(always)]
56 pub fn wakeup_enable(&self) -> WAKEUP_ENABLE_R {
57 WAKEUP_ENABLE_R::new(((self.bits >> 10) & 1) != 0)
58 }
59 #[doc = "Bits 11:12 - reserved"]
60 #[inline(always)]
61 pub fn config(&self) -> CONFIG_R {
62 CONFIG_R::new(((self.bits >> 11) & 3) as u8)
63 }
64 #[doc = "Bits 13:17 - set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt."]
65 #[inline(always)]
66 pub fn int_ena(&self) -> INT_ENA_R {
67 INT_ENA_R::new(((self.bits >> 13) & 0x1f) as u8)
68 }
69}
70#[cfg(feature = "impl-register-debug")]
71impl core::fmt::Debug for R {
72 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
73 f.debug_struct("PIN")
74 .field("sync2_bypass", &self.sync2_bypass())
75 .field("pad_driver", &self.pad_driver())
76 .field("sync1_bypass", &self.sync1_bypass())
77 .field("int_type", &self.int_type())
78 .field("wakeup_enable", &self.wakeup_enable())
79 .field("config", &self.config())
80 .field("int_ena", &self.int_ena())
81 .finish()
82 }
83}
84impl W {
85 #[doc = "Bits 0:1 - set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge."]
86 #[inline(always)]
87 pub fn sync2_bypass(&mut self) -> SYNC2_BYPASS_W<PIN_SPEC> {
88 SYNC2_BYPASS_W::new(self, 0)
89 }
90 #[doc = "Bit 2 - set this bit to select pad driver. 1:open-drain. 0:normal."]
91 #[inline(always)]
92 pub fn pad_driver(&mut self) -> PAD_DRIVER_W<PIN_SPEC> {
93 PAD_DRIVER_W::new(self, 2)
94 }
95 #[doc = "Bits 3:4 - set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge."]
96 #[inline(always)]
97 pub fn sync1_bypass(&mut self) -> SYNC1_BYPASS_W<PIN_SPEC> {
98 SYNC1_BYPASS_W::new(self, 3)
99 }
100 #[doc = "Bits 7:9 - set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level"]
101 #[inline(always)]
102 pub fn int_type(&mut self) -> INT_TYPE_W<PIN_SPEC> {
103 INT_TYPE_W::new(self, 7)
104 }
105 #[doc = "Bit 10 - set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)"]
106 #[inline(always)]
107 pub fn wakeup_enable(&mut self) -> WAKEUP_ENABLE_W<PIN_SPEC> {
108 WAKEUP_ENABLE_W::new(self, 10)
109 }
110 #[doc = "Bits 11:12 - reserved"]
111 #[inline(always)]
112 pub fn config(&mut self) -> CONFIG_W<PIN_SPEC> {
113 CONFIG_W::new(self, 11)
114 }
115 #[doc = "Bits 13:17 - set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt."]
116 #[inline(always)]
117 pub fn int_ena(&mut self) -> INT_ENA_W<PIN_SPEC> {
118 INT_ENA_W::new(self, 13)
119 }
120}
121#[doc = "GPIO pin configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`pin::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
122pub struct PIN_SPEC;
123impl crate::RegisterSpec for PIN_SPEC {
124 type Ux = u32;
125}
126#[doc = "`read()` method returns [`pin::R`](R) reader structure"]
127impl crate::Readable for PIN_SPEC {}
128#[doc = "`write(|w| ..)` method takes [`pin::W`](W) writer structure"]
129impl crate::Writable for PIN_SPEC {
130 type Safety = crate::Unsafe;
131 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
132 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
133}
134#[doc = "`reset()` method sets PIN%s to value 0"]
135impl crate::Resettable for PIN_SPEC {
136 const RESET_VALUE: u32 = 0;
137}