esp32c2/dma/int_ch/
raw.rs1#[doc = "Register `RAW` reader"]
2pub type R = crate::R<RAW_SPEC>;
3#[doc = "Register `RAW` writer"]
4pub type W = crate::W<RAW_SPEC>;
5#[doc = "Field `IN_DONE` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0."]
6pub type IN_DONE_R = crate::BitReader;
7#[doc = "Field `IN_DONE` writer - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0."]
8pub type IN_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `IN_SUC_EOF` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0."]
10pub type IN_SUC_EOF_R = crate::BitReader;
11#[doc = "Field `IN_SUC_EOF` writer - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0."]
12pub type IN_SUC_EOF_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `IN_ERR_EOF` reader - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved."]
14pub type IN_ERR_EOF_R = crate::BitReader;
15#[doc = "Field `IN_ERR_EOF` writer - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved."]
16pub type IN_ERR_EOF_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `OUT_DONE` reader - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."]
18pub type OUT_DONE_R = crate::BitReader;
19#[doc = "Field `OUT_DONE` writer - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."]
20pub type OUT_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `OUT_EOF` reader - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."]
22pub type OUT_EOF_R = crate::BitReader;
23#[doc = "Field `OUT_EOF` writer - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."]
24pub type OUT_EOF_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `IN_DSCR_ERR` reader - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0."]
26pub type IN_DSCR_ERR_R = crate::BitReader;
27#[doc = "Field `IN_DSCR_ERR` writer - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0."]
28pub type IN_DSCR_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `OUT_DSCR_ERR` reader - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0."]
30pub type OUT_DSCR_ERR_R = crate::BitReader;
31#[doc = "Field `OUT_DSCR_ERR` writer - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0."]
32pub type OUT_DSCR_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `IN_DSCR_EMPTY` reader - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0."]
34pub type IN_DSCR_EMPTY_R = crate::BitReader;
35#[doc = "Field `IN_DSCR_EMPTY` writer - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0."]
36pub type IN_DSCR_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `OUT_TOTAL_EOF` reader - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."]
38pub type OUT_TOTAL_EOF_R = crate::BitReader;
39#[doc = "Field `OUT_TOTAL_EOF` writer - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."]
40pub type OUT_TOTAL_EOF_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `INFIFO_OVF` reader - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."]
42pub type INFIFO_OVF_R = crate::BitReader;
43#[doc = "Field `INFIFO_OVF` writer - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."]
44pub type INFIFO_OVF_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `INFIFO_UDF` reader - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."]
46pub type INFIFO_UDF_R = crate::BitReader;
47#[doc = "Field `INFIFO_UDF` writer - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."]
48pub type INFIFO_UDF_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `OUTFIFO_OVF` reader - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow."]
50pub type OUTFIFO_OVF_R = crate::BitReader;
51#[doc = "Field `OUTFIFO_OVF` writer - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow."]
52pub type OUTFIFO_OVF_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `OUTFIFO_UDF` reader - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow."]
54pub type OUTFIFO_UDF_R = crate::BitReader;
55#[doc = "Field `OUTFIFO_UDF` writer - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow."]
56pub type OUTFIFO_UDF_W<'a, REG> = crate::BitWriter<'a, REG>;
57impl R {
58 #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0."]
59 #[inline(always)]
60 pub fn in_done(&self) -> IN_DONE_R {
61 IN_DONE_R::new((self.bits & 1) != 0)
62 }
63 #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0."]
64 #[inline(always)]
65 pub fn in_suc_eof(&self) -> IN_SUC_EOF_R {
66 IN_SUC_EOF_R::new(((self.bits >> 1) & 1) != 0)
67 }
68 #[doc = "Bit 2 - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved."]
69 #[inline(always)]
70 pub fn in_err_eof(&self) -> IN_ERR_EOF_R {
71 IN_ERR_EOF_R::new(((self.bits >> 2) & 1) != 0)
72 }
73 #[doc = "Bit 3 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."]
74 #[inline(always)]
75 pub fn out_done(&self) -> OUT_DONE_R {
76 OUT_DONE_R::new(((self.bits >> 3) & 1) != 0)
77 }
78 #[doc = "Bit 4 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."]
79 #[inline(always)]
80 pub fn out_eof(&self) -> OUT_EOF_R {
81 OUT_EOF_R::new(((self.bits >> 4) & 1) != 0)
82 }
83 #[doc = "Bit 5 - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0."]
84 #[inline(always)]
85 pub fn in_dscr_err(&self) -> IN_DSCR_ERR_R {
86 IN_DSCR_ERR_R::new(((self.bits >> 5) & 1) != 0)
87 }
88 #[doc = "Bit 6 - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0."]
89 #[inline(always)]
90 pub fn out_dscr_err(&self) -> OUT_DSCR_ERR_R {
91 OUT_DSCR_ERR_R::new(((self.bits >> 6) & 1) != 0)
92 }
93 #[doc = "Bit 7 - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0."]
94 #[inline(always)]
95 pub fn in_dscr_empty(&self) -> IN_DSCR_EMPTY_R {
96 IN_DSCR_EMPTY_R::new(((self.bits >> 7) & 1) != 0)
97 }
98 #[doc = "Bit 8 - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."]
99 #[inline(always)]
100 pub fn out_total_eof(&self) -> OUT_TOTAL_EOF_R {
101 OUT_TOTAL_EOF_R::new(((self.bits >> 8) & 1) != 0)
102 }
103 #[doc = "Bit 9 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."]
104 #[inline(always)]
105 pub fn infifo_ovf(&self) -> INFIFO_OVF_R {
106 INFIFO_OVF_R::new(((self.bits >> 9) & 1) != 0)
107 }
108 #[doc = "Bit 10 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."]
109 #[inline(always)]
110 pub fn infifo_udf(&self) -> INFIFO_UDF_R {
111 INFIFO_UDF_R::new(((self.bits >> 10) & 1) != 0)
112 }
113 #[doc = "Bit 11 - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow."]
114 #[inline(always)]
115 pub fn outfifo_ovf(&self) -> OUTFIFO_OVF_R {
116 OUTFIFO_OVF_R::new(((self.bits >> 11) & 1) != 0)
117 }
118 #[doc = "Bit 12 - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow."]
119 #[inline(always)]
120 pub fn outfifo_udf(&self) -> OUTFIFO_UDF_R {
121 OUTFIFO_UDF_R::new(((self.bits >> 12) & 1) != 0)
122 }
123}
124#[cfg(feature = "impl-register-debug")]
125impl core::fmt::Debug for R {
126 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
127 f.debug_struct("RAW")
128 .field("in_done", &self.in_done())
129 .field("in_suc_eof", &self.in_suc_eof())
130 .field("in_err_eof", &self.in_err_eof())
131 .field("out_done", &self.out_done())
132 .field("out_eof", &self.out_eof())
133 .field("in_dscr_err", &self.in_dscr_err())
134 .field("out_dscr_err", &self.out_dscr_err())
135 .field("in_dscr_empty", &self.in_dscr_empty())
136 .field("out_total_eof", &self.out_total_eof())
137 .field("infifo_ovf", &self.infifo_ovf())
138 .field("infifo_udf", &self.infifo_udf())
139 .field("outfifo_ovf", &self.outfifo_ovf())
140 .field("outfifo_udf", &self.outfifo_udf())
141 .finish()
142 }
143}
144impl W {
145 #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0."]
146 #[inline(always)]
147 pub fn in_done(&mut self) -> IN_DONE_W<RAW_SPEC> {
148 IN_DONE_W::new(self, 0)
149 }
150 #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0."]
151 #[inline(always)]
152 pub fn in_suc_eof(&mut self) -> IN_SUC_EOF_W<RAW_SPEC> {
153 IN_SUC_EOF_W::new(self, 1)
154 }
155 #[doc = "Bit 2 - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved."]
156 #[inline(always)]
157 pub fn in_err_eof(&mut self) -> IN_ERR_EOF_W<RAW_SPEC> {
158 IN_ERR_EOF_W::new(self, 2)
159 }
160 #[doc = "Bit 3 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."]
161 #[inline(always)]
162 pub fn out_done(&mut self) -> OUT_DONE_W<RAW_SPEC> {
163 OUT_DONE_W::new(self, 3)
164 }
165 #[doc = "Bit 4 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."]
166 #[inline(always)]
167 pub fn out_eof(&mut self) -> OUT_EOF_W<RAW_SPEC> {
168 OUT_EOF_W::new(self, 4)
169 }
170 #[doc = "Bit 5 - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0."]
171 #[inline(always)]
172 pub fn in_dscr_err(&mut self) -> IN_DSCR_ERR_W<RAW_SPEC> {
173 IN_DSCR_ERR_W::new(self, 5)
174 }
175 #[doc = "Bit 6 - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0."]
176 #[inline(always)]
177 pub fn out_dscr_err(&mut self) -> OUT_DSCR_ERR_W<RAW_SPEC> {
178 OUT_DSCR_ERR_W::new(self, 6)
179 }
180 #[doc = "Bit 7 - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0."]
181 #[inline(always)]
182 pub fn in_dscr_empty(&mut self) -> IN_DSCR_EMPTY_W<RAW_SPEC> {
183 IN_DSCR_EMPTY_W::new(self, 7)
184 }
185 #[doc = "Bit 8 - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."]
186 #[inline(always)]
187 pub fn out_total_eof(&mut self) -> OUT_TOTAL_EOF_W<RAW_SPEC> {
188 OUT_TOTAL_EOF_W::new(self, 8)
189 }
190 #[doc = "Bit 9 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."]
191 #[inline(always)]
192 pub fn infifo_ovf(&mut self) -> INFIFO_OVF_W<RAW_SPEC> {
193 INFIFO_OVF_W::new(self, 9)
194 }
195 #[doc = "Bit 10 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."]
196 #[inline(always)]
197 pub fn infifo_udf(&mut self) -> INFIFO_UDF_W<RAW_SPEC> {
198 INFIFO_UDF_W::new(self, 10)
199 }
200 #[doc = "Bit 11 - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow."]
201 #[inline(always)]
202 pub fn outfifo_ovf(&mut self) -> OUTFIFO_OVF_W<RAW_SPEC> {
203 OUTFIFO_OVF_W::new(self, 11)
204 }
205 #[doc = "Bit 12 - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow."]
206 #[inline(always)]
207 pub fn outfifo_udf(&mut self) -> OUTFIFO_UDF_W<RAW_SPEC> {
208 OUTFIFO_UDF_W::new(self, 12)
209 }
210}
211#[doc = "DMA_INT_RAW_CH0_REG.\n\nYou can [`read`](crate::Reg::read) this register and get [`raw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`raw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
212pub struct RAW_SPEC;
213impl crate::RegisterSpec for RAW_SPEC {
214 type Ux = u32;
215}
216#[doc = "`read()` method returns [`raw::R`](R) reader structure"]
217impl crate::Readable for RAW_SPEC {}
218#[doc = "`write(|w| ..)` method takes [`raw::W`](W) writer structure"]
219impl crate::Writable for RAW_SPEC {
220 type Safety = crate::Unsafe;
221 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
222 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
223}
224#[doc = "`reset()` method sets RAW to value 0"]
225impl crate::Resettable for RAW_SPEC {
226 const RESET_VALUE: u32 = 0;
227}