Module sha

SHA (Secure Hash Algorithm) Accelerator

Modules

busy

Busy register.

clear_irq

Interrupt clear register.

continue_

Typical SHA configuration register 1.

date

Date register.

dma_block_num

DMA configuration register 0.

dma_continue

DMA configuration register 2.

dma_start

DMA configuration register 1.

h_mem

Sha H memory which contains intermediate hash or finial hash.

irq_ena

Interrupt enable register.

m_mem

Sha M memory which contains message.

mode

Initial configuration register.

start

Typical SHA configuration register 0.

t_length

SHA 512/t configuration register 1.

t_string

SHA 512/t configuration register 0.

Structs

RegisterBlock

Register block

Type Aliases

BUSY

BUSY (r) register accessor: Busy register.

CLEAR_IRQ

CLEAR_IRQ (w) register accessor: Interrupt clear register.

CONTINUE

CONTINUE (w) register accessor: Typical SHA configuration register 1.

DATE

DATE (rw) register accessor: Date register.

DMA_BLOCK_NUM

DMA_BLOCK_NUM (rw) register accessor: DMA configuration register 0.

DMA_CONTINUE

DMA_CONTINUE (w) register accessor: DMA configuration register 2.

DMA_START

DMA_START (w) register accessor: DMA configuration register 1.

H_MEM

H_MEM (rw) register accessor: Sha H memory which contains intermediate hash or finial hash.

IRQ_ENA

IRQ_ENA (rw) register accessor: Interrupt enable register.

MODE

MODE (rw) register accessor: Initial configuration register.

M_MEM

M_MEM (rw) register accessor: Sha M memory which contains message.

START

START (w) register accessor: Typical SHA configuration register 0.

T_LENGTH

T_LENGTH (rw) register accessor: SHA 512/t configuration register 1.

T_STRING

T_STRING (rw) register accessor: SHA 512/t configuration register 0.