esp32/spi0/
user1.rs

1#[doc = "Register `USER1` reader"]
2pub type R = crate::R<USER1_SPEC>;
3#[doc = "Register `USER1` writer"]
4pub type W = crate::W<USER1_SPEC>;
5#[doc = "Field `USR_DUMMY_CYCLELEN` reader - The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1)."]
6pub type USR_DUMMY_CYCLELEN_R = crate::FieldReader;
7#[doc = "Field `USR_DUMMY_CYCLELEN` writer - The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1)."]
8pub type USR_DUMMY_CYCLELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `USR_ADDR_BITLEN` reader - The length in bits of address phase. The register value shall be (bit_num-1)."]
10pub type USR_ADDR_BITLEN_R = crate::FieldReader;
11#[doc = "Field `USR_ADDR_BITLEN` writer - The length in bits of address phase. The register value shall be (bit_num-1)."]
12pub type USR_ADDR_BITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
13impl R {
14    #[doc = "Bits 0:7 - The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1)."]
15    #[inline(always)]
16    pub fn usr_dummy_cyclelen(&self) -> USR_DUMMY_CYCLELEN_R {
17        USR_DUMMY_CYCLELEN_R::new((self.bits & 0xff) as u8)
18    }
19    #[doc = "Bits 26:31 - The length in bits of address phase. The register value shall be (bit_num-1)."]
20    #[inline(always)]
21    pub fn usr_addr_bitlen(&self) -> USR_ADDR_BITLEN_R {
22        USR_ADDR_BITLEN_R::new(((self.bits >> 26) & 0x3f) as u8)
23    }
24}
25#[cfg(feature = "impl-register-debug")]
26impl core::fmt::Debug for R {
27    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
28        f.debug_struct("USER1")
29            .field("usr_dummy_cyclelen", &self.usr_dummy_cyclelen())
30            .field("usr_addr_bitlen", &self.usr_addr_bitlen())
31            .finish()
32    }
33}
34impl W {
35    #[doc = "Bits 0:7 - The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1)."]
36    #[inline(always)]
37    pub fn usr_dummy_cyclelen(&mut self) -> USR_DUMMY_CYCLELEN_W<USER1_SPEC> {
38        USR_DUMMY_CYCLELEN_W::new(self, 0)
39    }
40    #[doc = "Bits 26:31 - The length in bits of address phase. The register value shall be (bit_num-1)."]
41    #[inline(always)]
42    pub fn usr_addr_bitlen(&mut self) -> USR_ADDR_BITLEN_W<USER1_SPEC> {
43        USR_ADDR_BITLEN_W::new(self, 26)
44    }
45}
46#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`user1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`user1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
47pub struct USER1_SPEC;
48impl crate::RegisterSpec for USER1_SPEC {
49    type Ux = u32;
50}
51#[doc = "`read()` method returns [`user1::R`](R) reader structure"]
52impl crate::Readable for USER1_SPEC {}
53#[doc = "`write(|w| ..)` method takes [`user1::W`](W) writer structure"]
54impl crate::Writable for USER1_SPEC {
55    type Safety = crate::Unsafe;
56    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
57    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
58}
59#[doc = "`reset()` method sets USER1 to value 0x5c00_0007"]
60impl crate::Resettable for USER1_SPEC {
61    const RESET_VALUE: u32 = 0x5c00_0007;
62}
esp32/spi0/user1.rs

esp32/spi0/
user1.rs
