1#[doc = "Register `INT_CLR` writer"]
2pub type W = crate::W<INT_CLR_SPEC>;
3#[doc = "Field `CH_TX_END(0-7)` writer - Set this bit to clear the rmt_ch%s_rx_end_int_raw.."]
4pub type CH_TX_END_W<'a, REG> = crate::BitWriter<'a, REG>;
5#[doc = "Field `CH_RX_END(0-7)` writer - Set this bit to clear the rmt_ch%s_tx_end_int_raw."]
6pub type CH_RX_END_W<'a, REG> = crate::BitWriter<'a, REG>;
7#[doc = "Field `CH_ERR(0-7)` writer - Set this bit to clear the rmt_ch%s_err_int_raw."]
8pub type CH_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CH_TX_THR_EVENT(0-7)` writer - Set this bit to clear the rmt_ch%s_tx_thr_event_int_raw interrupt."]
10pub type CH_TX_THR_EVENT_W<'a, REG> = crate::BitWriter<'a, REG>;
11#[cfg(feature = "impl-register-debug")]
12impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
13 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
14 write!(f, "(not readable)")
15 }
16}
17impl W {
18 #[doc = "Set this bit to clear the rmt_ch(0-7)_rx_end_int_raw.."]
19 #[doc = ""]
20 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_END` field.</div>"]
21 #[inline(always)]
22 pub fn ch_tx_end(&mut self, n: u8) -> CH_TX_END_W<INT_CLR_SPEC> {
23 #[allow(clippy::no_effect)]
24 [(); 8][n as usize];
25 CH_TX_END_W::new(self, n * 3)
26 }
27 #[doc = "Bit 0 - Set this bit to clear the rmt_ch0_rx_end_int_raw.."]
28 #[inline(always)]
29 pub fn ch0_tx_end(&mut self) -> CH_TX_END_W<INT_CLR_SPEC> {
30 CH_TX_END_W::new(self, 0)
31 }
32 #[doc = "Bit 3 - Set this bit to clear the rmt_ch1_rx_end_int_raw.."]
33 #[inline(always)]
34 pub fn ch1_tx_end(&mut self) -> CH_TX_END_W<INT_CLR_SPEC> {
35 CH_TX_END_W::new(self, 3)
36 }
37 #[doc = "Bit 6 - Set this bit to clear the rmt_ch2_rx_end_int_raw.."]
38 #[inline(always)]
39 pub fn ch2_tx_end(&mut self) -> CH_TX_END_W<INT_CLR_SPEC> {
40 CH_TX_END_W::new(self, 6)
41 }
42 #[doc = "Bit 9 - Set this bit to clear the rmt_ch3_rx_end_int_raw.."]
43 #[inline(always)]
44 pub fn ch3_tx_end(&mut self) -> CH_TX_END_W<INT_CLR_SPEC> {
45 CH_TX_END_W::new(self, 9)
46 }
47 #[doc = "Bit 12 - Set this bit to clear the rmt_ch4_rx_end_int_raw.."]
48 #[inline(always)]
49 pub fn ch4_tx_end(&mut self) -> CH_TX_END_W<INT_CLR_SPEC> {
50 CH_TX_END_W::new(self, 12)
51 }
52 #[doc = "Bit 15 - Set this bit to clear the rmt_ch5_rx_end_int_raw.."]
53 #[inline(always)]
54 pub fn ch5_tx_end(&mut self) -> CH_TX_END_W<INT_CLR_SPEC> {
55 CH_TX_END_W::new(self, 15)
56 }
57 #[doc = "Bit 18 - Set this bit to clear the rmt_ch6_rx_end_int_raw.."]
58 #[inline(always)]
59 pub fn ch6_tx_end(&mut self) -> CH_TX_END_W<INT_CLR_SPEC> {
60 CH_TX_END_W::new(self, 18)
61 }
62 #[doc = "Bit 21 - Set this bit to clear the rmt_ch7_rx_end_int_raw.."]
63 #[inline(always)]
64 pub fn ch7_tx_end(&mut self) -> CH_TX_END_W<INT_CLR_SPEC> {
65 CH_TX_END_W::new(self, 21)
66 }
67 #[doc = "Set this bit to clear the rmt_ch(0-7)_tx_end_int_raw."]
68 #[doc = ""]
69 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_RX_END` field.</div>"]
70 #[inline(always)]
71 pub fn ch_rx_end(&mut self, n: u8) -> CH_RX_END_W<INT_CLR_SPEC> {
72 #[allow(clippy::no_effect)]
73 [(); 8][n as usize];
74 CH_RX_END_W::new(self, n * 3 + 1)
75 }
76 #[doc = "Bit 1 - Set this bit to clear the rmt_ch0_tx_end_int_raw."]
77 #[inline(always)]
78 pub fn ch0_rx_end(&mut self) -> CH_RX_END_W<INT_CLR_SPEC> {
79 CH_RX_END_W::new(self, 1)
80 }
81 #[doc = "Bit 4 - Set this bit to clear the rmt_ch1_tx_end_int_raw."]
82 #[inline(always)]
83 pub fn ch1_rx_end(&mut self) -> CH_RX_END_W<INT_CLR_SPEC> {
84 CH_RX_END_W::new(self, 4)
85 }
86 #[doc = "Bit 7 - Set this bit to clear the rmt_ch2_tx_end_int_raw."]
87 #[inline(always)]
88 pub fn ch2_rx_end(&mut self) -> CH_RX_END_W<INT_CLR_SPEC> {
89 CH_RX_END_W::new(self, 7)
90 }
91 #[doc = "Bit 10 - Set this bit to clear the rmt_ch3_tx_end_int_raw."]
92 #[inline(always)]
93 pub fn ch3_rx_end(&mut self) -> CH_RX_END_W<INT_CLR_SPEC> {
94 CH_RX_END_W::new(self, 10)
95 }
96 #[doc = "Bit 13 - Set this bit to clear the rmt_ch4_tx_end_int_raw."]
97 #[inline(always)]
98 pub fn ch4_rx_end(&mut self) -> CH_RX_END_W<INT_CLR_SPEC> {
99 CH_RX_END_W::new(self, 13)
100 }
101 #[doc = "Bit 16 - Set this bit to clear the rmt_ch5_tx_end_int_raw."]
102 #[inline(always)]
103 pub fn ch5_rx_end(&mut self) -> CH_RX_END_W<INT_CLR_SPEC> {
104 CH_RX_END_W::new(self, 16)
105 }
106 #[doc = "Bit 19 - Set this bit to clear the rmt_ch6_tx_end_int_raw."]
107 #[inline(always)]
108 pub fn ch6_rx_end(&mut self) -> CH_RX_END_W<INT_CLR_SPEC> {
109 CH_RX_END_W::new(self, 19)
110 }
111 #[doc = "Bit 22 - Set this bit to clear the rmt_ch7_tx_end_int_raw."]
112 #[inline(always)]
113 pub fn ch7_rx_end(&mut self) -> CH_RX_END_W<INT_CLR_SPEC> {
114 CH_RX_END_W::new(self, 22)
115 }
116 #[doc = "Set this bit to clear the rmt_ch(0-7)_err_int_raw."]
117 #[doc = ""]
118 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_ERR` field.</div>"]
119 #[inline(always)]
120 pub fn ch_err(&mut self, n: u8) -> CH_ERR_W<INT_CLR_SPEC> {
121 #[allow(clippy::no_effect)]
122 [(); 8][n as usize];
123 CH_ERR_W::new(self, n * 3 + 2)
124 }
125 #[doc = "Bit 2 - Set this bit to clear the rmt_ch0_err_int_raw."]
126 #[inline(always)]
127 pub fn ch0_err(&mut self) -> CH_ERR_W<INT_CLR_SPEC> {
128 CH_ERR_W::new(self, 2)
129 }
130 #[doc = "Bit 5 - Set this bit to clear the rmt_ch1_err_int_raw."]
131 #[inline(always)]
132 pub fn ch1_err(&mut self) -> CH_ERR_W<INT_CLR_SPEC> {
133 CH_ERR_W::new(self, 5)
134 }
135 #[doc = "Bit 8 - Set this bit to clear the rmt_ch2_err_int_raw."]
136 #[inline(always)]
137 pub fn ch2_err(&mut self) -> CH_ERR_W<INT_CLR_SPEC> {
138 CH_ERR_W::new(self, 8)
139 }
140 #[doc = "Bit 11 - Set this bit to clear the rmt_ch3_err_int_raw."]
141 #[inline(always)]
142 pub fn ch3_err(&mut self) -> CH_ERR_W<INT_CLR_SPEC> {
143 CH_ERR_W::new(self, 11)
144 }
145 #[doc = "Bit 14 - Set this bit to clear the rmt_ch4_err_int_raw."]
146 #[inline(always)]
147 pub fn ch4_err(&mut self) -> CH_ERR_W<INT_CLR_SPEC> {
148 CH_ERR_W::new(self, 14)
149 }
150 #[doc = "Bit 17 - Set this bit to clear the rmt_ch5_err_int_raw."]
151 #[inline(always)]
152 pub fn ch5_err(&mut self) -> CH_ERR_W<INT_CLR_SPEC> {
153 CH_ERR_W::new(self, 17)
154 }
155 #[doc = "Bit 20 - Set this bit to clear the rmt_ch6_err_int_raw."]
156 #[inline(always)]
157 pub fn ch6_err(&mut self) -> CH_ERR_W<INT_CLR_SPEC> {
158 CH_ERR_W::new(self, 20)
159 }
160 #[doc = "Bit 23 - Set this bit to clear the rmt_ch7_err_int_raw."]
161 #[inline(always)]
162 pub fn ch7_err(&mut self) -> CH_ERR_W<INT_CLR_SPEC> {
163 CH_ERR_W::new(self, 23)
164 }
165 #[doc = "Set this bit to clear the rmt_ch(0-7)_tx_thr_event_int_raw interrupt."]
166 #[doc = ""]
167 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_THR_EVENT` field.</div>"]
168 #[inline(always)]
169 pub fn ch_tx_thr_event(&mut self, n: u8) -> CH_TX_THR_EVENT_W<INT_CLR_SPEC> {
170 #[allow(clippy::no_effect)]
171 [(); 8][n as usize];
172 CH_TX_THR_EVENT_W::new(self, n + 24)
173 }
174 #[doc = "Bit 24 - Set this bit to clear the rmt_ch0_tx_thr_event_int_raw interrupt."]
175 #[inline(always)]
176 pub fn ch0_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_CLR_SPEC> {
177 CH_TX_THR_EVENT_W::new(self, 24)
178 }
179 #[doc = "Bit 25 - Set this bit to clear the rmt_ch1_tx_thr_event_int_raw interrupt."]
180 #[inline(always)]
181 pub fn ch1_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_CLR_SPEC> {
182 CH_TX_THR_EVENT_W::new(self, 25)
183 }
184 #[doc = "Bit 26 - Set this bit to clear the rmt_ch2_tx_thr_event_int_raw interrupt."]
185 #[inline(always)]
186 pub fn ch2_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_CLR_SPEC> {
187 CH_TX_THR_EVENT_W::new(self, 26)
188 }
189 #[doc = "Bit 27 - Set this bit to clear the rmt_ch3_tx_thr_event_int_raw interrupt."]
190 #[inline(always)]
191 pub fn ch3_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_CLR_SPEC> {
192 CH_TX_THR_EVENT_W::new(self, 27)
193 }
194 #[doc = "Bit 28 - Set this bit to clear the rmt_ch4_tx_thr_event_int_raw interrupt."]
195 #[inline(always)]
196 pub fn ch4_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_CLR_SPEC> {
197 CH_TX_THR_EVENT_W::new(self, 28)
198 }
199 #[doc = "Bit 29 - Set this bit to clear the rmt_ch5_tx_thr_event_int_raw interrupt."]
200 #[inline(always)]
201 pub fn ch5_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_CLR_SPEC> {
202 CH_TX_THR_EVENT_W::new(self, 29)
203 }
204 #[doc = "Bit 30 - Set this bit to clear the rmt_ch6_tx_thr_event_int_raw interrupt."]
205 #[inline(always)]
206 pub fn ch6_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_CLR_SPEC> {
207 CH_TX_THR_EVENT_W::new(self, 30)
208 }
209 #[doc = "Bit 31 - Set this bit to clear the rmt_ch7_tx_thr_event_int_raw interrupt."]
210 #[inline(always)]
211 pub fn ch7_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_CLR_SPEC> {
212 CH_TX_THR_EVENT_W::new(self, 31)
213 }
214}
215#[doc = "\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
216pub struct INT_CLR_SPEC;
217impl crate::RegisterSpec for INT_CLR_SPEC {
218 type Ux = u32;
219}
220#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
221impl crate::Writable for INT_CLR_SPEC {
222 type Safety = crate::Unsafe;
223 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
224 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
225}
226#[doc = "`reset()` method sets INT_CLR to value 0"]
227impl crate::Resettable for INT_CLR_SPEC {
228 const RESET_VALUE: u32 = 0;
229}