1#[doc = "Register `PIN%s` reader"]
2pub type R = crate::R<PIN_SPEC>;
3#[doc = "Register `PIN%s` writer"]
4pub type W = crate::W<PIN_SPEC>;
5#[doc = "Field `PAD_DRIVER` reader - if set to 0: normal output if set to 1: open drain"]
6pub type PAD_DRIVER_R = crate::BitReader;
7#[doc = "Field `PAD_DRIVER` writer - if set to 0: normal output if set to 1: open drain"]
8pub type PAD_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `INT_TYPE` reader - if set to 0: GPIO interrupt disable if set to 1: rising edge trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger"]
10pub type INT_TYPE_R = crate::FieldReader;
11#[doc = "Field `INT_TYPE` writer - if set to 0: GPIO interrupt disable if set to 1: rising edge trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger"]
12pub type INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
13#[doc = "Field `WAKEUP_ENABLE` reader - GPIO wake up enable only available in light sleep"]
14pub type WAKEUP_ENABLE_R = crate::BitReader;
15#[doc = "Field `WAKEUP_ENABLE` writer - GPIO wake up enable only available in light sleep"]
16pub type WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `CONFIG` reader - NA"]
18pub type CONFIG_R = crate::FieldReader;
19#[doc = "Field `CONFIG` writer - NA"]
20pub type CONFIG_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
21#[doc = "Field `INT_ENA` reader - bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable"]
22pub type INT_ENA_R = crate::FieldReader;
23#[doc = "Field `INT_ENA` writer - bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable"]
24pub type INT_ENA_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
25impl R {
26 #[doc = "Bit 2 - if set to 0: normal output if set to 1: open drain"]
27 #[inline(always)]
28 pub fn pad_driver(&self) -> PAD_DRIVER_R {
29 PAD_DRIVER_R::new(((self.bits >> 2) & 1) != 0)
30 }
31 #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable if set to 1: rising edge trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger"]
32 #[inline(always)]
33 pub fn int_type(&self) -> INT_TYPE_R {
34 INT_TYPE_R::new(((self.bits >> 7) & 7) as u8)
35 }
36 #[doc = "Bit 10 - GPIO wake up enable only available in light sleep"]
37 #[inline(always)]
38 pub fn wakeup_enable(&self) -> WAKEUP_ENABLE_R {
39 WAKEUP_ENABLE_R::new(((self.bits >> 10) & 1) != 0)
40 }
41 #[doc = "Bits 11:12 - NA"]
42 #[inline(always)]
43 pub fn config(&self) -> CONFIG_R {
44 CONFIG_R::new(((self.bits >> 11) & 3) as u8)
45 }
46 #[doc = "Bits 13:17 - bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable"]
47 #[inline(always)]
48 pub fn int_ena(&self) -> INT_ENA_R {
49 INT_ENA_R::new(((self.bits >> 13) & 0x1f) as u8)
50 }
51}
52#[cfg(feature = "impl-register-debug")]
53impl core::fmt::Debug for R {
54 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
55 f.debug_struct("PIN")
56 .field("pad_driver", &self.pad_driver())
57 .field("int_type", &self.int_type())
58 .field("wakeup_enable", &self.wakeup_enable())
59 .field("config", &self.config())
60 .field("int_ena", &self.int_ena())
61 .finish()
62 }
63}
64impl W {
65 #[doc = "Bit 2 - if set to 0: normal output if set to 1: open drain"]
66 #[inline(always)]
67 pub fn pad_driver(&mut self) -> PAD_DRIVER_W<PIN_SPEC> {
68 PAD_DRIVER_W::new(self, 2)
69 }
70 #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable if set to 1: rising edge trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger"]
71 #[inline(always)]
72 pub fn int_type(&mut self) -> INT_TYPE_W<PIN_SPEC> {
73 INT_TYPE_W::new(self, 7)
74 }
75 #[doc = "Bit 10 - GPIO wake up enable only available in light sleep"]
76 #[inline(always)]
77 pub fn wakeup_enable(&mut self) -> WAKEUP_ENABLE_W<PIN_SPEC> {
78 WAKEUP_ENABLE_W::new(self, 10)
79 }
80 #[doc = "Bits 11:12 - NA"]
81 #[inline(always)]
82 pub fn config(&mut self) -> CONFIG_W<PIN_SPEC> {
83 CONFIG_W::new(self, 11)
84 }
85 #[doc = "Bits 13:17 - bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable"]
86 #[inline(always)]
87 pub fn int_ena(&mut self) -> INT_ENA_W<PIN_SPEC> {
88 INT_ENA_W::new(self, 13)
89 }
90}
91#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`pin::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
92pub struct PIN_SPEC;
93impl crate::RegisterSpec for PIN_SPEC {
94 type Ux = u32;
95}
96#[doc = "`read()` method returns [`pin::R`](R) reader structure"]
97impl crate::Readable for PIN_SPEC {}
98#[doc = "`write(|w| ..)` method takes [`pin::W`](W) writer structure"]
99impl crate::Writable for PIN_SPEC {
100 type Safety = crate::Unsafe;
101 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
102 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
103}
104#[doc = "`reset()` method sets PIN%s to value 0"]
105impl crate::Resettable for PIN_SPEC {
106 const RESET_VALUE: u32 = 0;
107}