esp32/apb_ctrl/
sysclk_conf.rs

1#[doc = "Register `SYSCLK_CONF` reader"]
2pub type R = crate::R<SYSCLK_CONF_SPEC>;
3#[doc = "Register `SYSCLK_CONF` writer"]
4pub type W = crate::W<SYSCLK_CONF_SPEC>;
5#[doc = "Field `PRE_DIV_CNT` reader - "]
6pub type PRE_DIV_CNT_R = crate::FieldReader<u16>;
7#[doc = "Field `PRE_DIV_CNT` writer - "]
8pub type PRE_DIV_CNT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
9#[doc = "Field `CLK_320M_EN` reader - "]
10pub type CLK_320M_EN_R = crate::BitReader;
11#[doc = "Field `CLK_320M_EN` writer - "]
12pub type CLK_320M_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CLK_EN` reader - "]
14pub type CLK_EN_R = crate::BitReader;
15#[doc = "Field `CLK_EN` writer - "]
16pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `RST_TICK_CNT` reader - "]
18pub type RST_TICK_CNT_R = crate::BitReader;
19#[doc = "Field `RST_TICK_CNT` writer - "]
20pub type RST_TICK_CNT_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `QUICK_CLK_CHNG` reader - "]
22pub type QUICK_CLK_CHNG_R = crate::BitReader;
23#[doc = "Field `QUICK_CLK_CHNG` writer - "]
24pub type QUICK_CLK_CHNG_W<'a, REG> = crate::BitWriter<'a, REG>;
25impl R {
26    #[doc = "Bits 0:9"]
27    #[inline(always)]
28    pub fn pre_div_cnt(&self) -> PRE_DIV_CNT_R {
29        PRE_DIV_CNT_R::new((self.bits & 0x03ff) as u16)
30    }
31    #[doc = "Bit 10"]
32    #[inline(always)]
33    pub fn clk_320m_en(&self) -> CLK_320M_EN_R {
34        CLK_320M_EN_R::new(((self.bits >> 10) & 1) != 0)
35    }
36    #[doc = "Bit 11"]
37    #[inline(always)]
38    pub fn clk_en(&self) -> CLK_EN_R {
39        CLK_EN_R::new(((self.bits >> 11) & 1) != 0)
40    }
41    #[doc = "Bit 12"]
42    #[inline(always)]
43    pub fn rst_tick_cnt(&self) -> RST_TICK_CNT_R {
44        RST_TICK_CNT_R::new(((self.bits >> 12) & 1) != 0)
45    }
46    #[doc = "Bit 13"]
47    #[inline(always)]
48    pub fn quick_clk_chng(&self) -> QUICK_CLK_CHNG_R {
49        QUICK_CLK_CHNG_R::new(((self.bits >> 13) & 1) != 0)
50    }
51}
52#[cfg(feature = "impl-register-debug")]
53impl core::fmt::Debug for R {
54    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
55        f.debug_struct("SYSCLK_CONF")
56            .field("pre_div_cnt", &self.pre_div_cnt())
57            .field("clk_320m_en", &self.clk_320m_en())
58            .field("clk_en", &self.clk_en())
59            .field("rst_tick_cnt", &self.rst_tick_cnt())
60            .field("quick_clk_chng", &self.quick_clk_chng())
61            .finish()
62    }
63}
64impl W {
65    #[doc = "Bits 0:9"]
66    #[inline(always)]
67    pub fn pre_div_cnt(&mut self) -> PRE_DIV_CNT_W<SYSCLK_CONF_SPEC> {
68        PRE_DIV_CNT_W::new(self, 0)
69    }
70    #[doc = "Bit 10"]
71    #[inline(always)]
72    pub fn clk_320m_en(&mut self) -> CLK_320M_EN_W<SYSCLK_CONF_SPEC> {
73        CLK_320M_EN_W::new(self, 10)
74    }
75    #[doc = "Bit 11"]
76    #[inline(always)]
77    pub fn clk_en(&mut self) -> CLK_EN_W<SYSCLK_CONF_SPEC> {
78        CLK_EN_W::new(self, 11)
79    }
80    #[doc = "Bit 12"]
81    #[inline(always)]
82    pub fn rst_tick_cnt(&mut self) -> RST_TICK_CNT_W<SYSCLK_CONF_SPEC> {
83        RST_TICK_CNT_W::new(self, 12)
84    }
85    #[doc = "Bit 13"]
86    #[inline(always)]
87    pub fn quick_clk_chng(&mut self) -> QUICK_CLK_CHNG_W<SYSCLK_CONF_SPEC> {
88        QUICK_CLK_CHNG_W::new(self, 13)
89    }
90}
91#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`sysclk_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sysclk_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
92pub struct SYSCLK_CONF_SPEC;
93impl crate::RegisterSpec for SYSCLK_CONF_SPEC {
94    type Ux = u32;
95}
96#[doc = "`read()` method returns [`sysclk_conf::R`](R) reader structure"]
97impl crate::Readable for SYSCLK_CONF_SPEC {}
98#[doc = "`write(|w| ..)` method takes [`sysclk_conf::W`](W) writer structure"]
99impl crate::Writable for SYSCLK_CONF_SPEC {
100    type Safety = crate::Unsafe;
101    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
102    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
103}
104#[doc = "`reset()` method sets SYSCLK_CONF to value 0x2000"]
105impl crate::Resettable for SYSCLK_CONF_SPEC {
106    const RESET_VALUE: u32 = 0x2000;
107}
esp32/apb_ctrl/sysclk_conf.rs

esp32/apb_ctrl/
sysclk_conf.rs
