Expand description
Ethernet Clock, PHY type, and SRAM configuration registers
Modules§
- ex_
clk_ ctrl - Clock enable and external/internal clock selection
- ex_
clkout_ conf - RMII clock divider setting
- ex_date
- ex_
oscclk_ conf - RMII clock half and whole divider settings
- ex_
phyinf_ conf - Selection of MII/RMII phy
- pd_sel
- Ethernet RAM power-down enable
Structs§
- Register
Block - Register block
Type Aliases§
- EX_
CLKOUT_ CONF - EX_CLKOUT_CONF (rw) register accessor: RMII clock divider setting
- EX_
CLK_ CTRL - EX_CLK_CTRL (rw) register accessor: Clock enable and external/internal clock selection
- EX_DATE
- EX_DATE (rw) register accessor:
- EX_
OSCCLK_ CONF - EX_OSCCLK_CONF (rw) register accessor: RMII clock half and whole divider settings
- EX_
PHYINF_ CONF - EX_PHYINF_CONF (rw) register accessor: Selection of MII/RMII phy
- PD_SEL
- PD_SEL (rw) register accessor: Ethernet RAM power-down enable