Enum esp32::Interrupt

#[repr(u8)]pub enum Interrupt {
    WIFI_MAC_INTR,
    WIFI_MAC_NMI,
    WIFI_BB_INTR,
    BT_MAC_INTR,
    BT_BB_INTR,
    BT_BB_NMI,
    RWBT_INTR,
    RWBLE_INTR,
    RWBT_NMI,
    RWBLE_NMI,
    SLC0_INTR,
    SLC1_INTR,
    UHCI0_INTR,
    UHCI1_INTR,
    TG0_T0_LEVEL_INTR,
    TG0_T1_LEVEL_INTR,
    TG0_WDT_LEVEL_INTR,
    TG0_LACT_LEVEL_INTR,
    TG1_T0_LEVEL_INTR,
    TG1_T1_LEVEL_INTR,
    TG1_WDT_LEVEL_INTR,
    TG1_LACT_LEVEL_INTR,
    GPIO_INTR,
    GPIO_NMI,
    FROM_CPU_INTR0,
    FROM_CPU_INTR1,
    FROM_CPU_INTR2,
    FROM_CPU_INTR3,
    SPI0_INTR,
    SPI1_INTR,
    SPI2_INTR,
    SPI3_INTR,
    I2S0_INTR,
    I2S1_INTR,
    UART0_INTR,
    UART1_INTR,
    UART2_INTR,
    SDIO_HOST_INTR,
    ETH_MAC_INTR,
    PWM0_INTR,
    PWM1_INTR,
    PWM2_INTR,
    PWM3_INTR,
    LEDC_INTR,
    EFUSE_INTR,
    CAN_INTR,
    RTC_CORE_INTR,
    RMT_INTR,
    PCNT_INTR,
    I2C_EXT0_INTR,
    I2C_EXT1_INTR,
    RSA_INTR,
    SPI1_DMA_INTR,
    SPI2_DMA_INTR,
    SPI3_DMA_INTR,
    WDT_INTR,
    TIMER1_INTR,
    TIMER2_INTR,
    TG0_T0_EDGE_INTR,
    TG0_T1_EDGE_INTR,
    TG0_WDT_EDGE_INTR,
    TG0_LACT_EDGE_INTR,
    TG1_T0_EDGE_INTR,
    TG1_T1_EDGE_INTR,
    TG1_WDT_EDGE_INTR,
    TG1_LACT_EDGE_INTR,
    MMU_IA_INTR,
    MPU_IA_INTR,
    CACHE_IA_INTR,
    INTERNAL_TIMER0_INTR,
    INTERNAL_SOFTWARE_LEVEL_1_INTR,
    INTERNAL_PROFILING_INTR,
    INTERNAL_TIMER1_INTR,
    INTERNAL_TIMER2_INTR,
    INTERNAL_SOFTWARE_LEVEL_3_INTR,
}

Enumeration of all the interrupts

Variants

WIFI_MAC_INTR

0 - interrupt of WiFi MAC, level

WIFI_MAC_NMI

1 - interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI

WIFI_BB_INTR

2 - interrupt of WiFi BB, level, we can do some calibration

BT_MAC_INTR

3 - will be cancelled

BT_BB_INTR

4 - interrupt of BT BB, level

BT_BB_NMI

5 - interrupt of BT BB, NMI, use if BB have bug to fix in NMI

RWBT_INTR

6 - interrupt of RWBT, level

RWBLE_INTR

7 - interrupt of RWBLE, level

RWBT_NMI

8 - interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI

RWBLE_NMI

9 - interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI

SLC0_INTR

10 - interrupt of SLC0, level

SLC1_INTR

11 - interrupt of SLC1, level

UHCI0_INTR

12 - interrupt of UHCI0, level

UHCI1_INTR

13 - interrupt of UHCI1, level

TG0_T0_LEVEL_INTR

14 - interrupt of TIMER_GROUP0, TIMER0, level, we would like use EDGE for timer if permission

TG0_T1_LEVEL_INTR

15 - interrupt of TIMER_GROUP0, TIMER1, level, we would like use EDGE for timer if permission

TG0_WDT_LEVEL_INTR

16 - interrupt of TIMER_GROUP0, WATCHDOG, level

TG0_LACT_LEVEL_INTR

17 - interrupt of TIMER_GROUP0, LACT, level

TG1_T0_LEVEL_INTR

18 - interrupt of TIMER_GROUP1, TIMER0, level, we would like use EDGE for timer if permission

TG1_T1_LEVEL_INTR

19 - interrupt of TIMER_GROUP1, TIMER1, level, we would like use EDGE for timer if permission

TG1_WDT_LEVEL_INTR

20 - interrupt of TIMER_GROUP1, WATCHDOG, level

TG1_LACT_LEVEL_INTR

21 - interrupt of TIMER_GROUP1, LACT, level

GPIO_INTR

22 - interrupt of GPIO, level

GPIO_NMI

23 - interrupt of GPIO, NMI

FROM_CPU_INTR0

24 - interrupt0 generated from a CPU, level

FROM_CPU_INTR1

25 - interrupt1 generated from a CPU, level

FROM_CPU_INTR2

26 - interrupt2 generated from a CPU, level

FROM_CPU_INTR3

27 - interrupt3 generated from a CPU, level

SPI0_INTR

28 - interrupt of SPI0, level, SPI0 is for Cache Access, do not use this

SPI1_INTR

29 - interrupt of SPI1, level, SPI1 is for flash read/write, do not use this

SPI2_INTR

30 - interrupt of SPI2, level

SPI3_INTR

31 - interrupt of SPI3, level

I2S0_INTR

32 - interrupt of I2S0, level

I2S1_INTR

33 - interrupt of I2S1, level

UART0_INTR

34 - interrupt of UART0, level

UART1_INTR

35 - interrupt of UART1, level

UART2_INTR

36 - interrupt of UART2, level

SDIO_HOST_INTR

37 - interrupt of SD/SDIO/MMC HOST, level

ETH_MAC_INTR

38 - interrupt of ethernet mac, level

PWM0_INTR

39 - interrupt of PWM0, level, Reserved

PWM1_INTR

40 - interrupt of PWM1, level, Reserved

PWM2_INTR

41 - interrupt of PWM2, level

PWM3_INTR

42 - interrupt of PWM3, level

LEDC_INTR

43 - interrupt of LED PWM, level

EFUSE_INTR

44 - interrupt of efuse, level, not likely to use

CAN_INTR

45 - interrupt of can, level

RTC_CORE_INTR

46 - interrupt of rtc core, level, include rtc watchdog

RMT_INTR

47 - interrupt of remote controller, level

PCNT_INTR

48 - interrupt of pluse count, level

I2C_EXT0_INTR

49 - interrupt of I2C controller0, level

I2C_EXT1_INTR

50 - interrupt of I2C controller1, level

RSA_INTR

51 - interrupt of RSA accelerator, level

SPI1_DMA_INTR

52 - interrupt of SPI1 DMA, SPI1 is for flash read/write, do not use this

SPI2_DMA_INTR

53 - interrupt of SPI2 DMA, level

SPI3_DMA_INTR

54 - interrupt of SPI3 DMA, level

WDT_INTR

55 - will be cancelled

TIMER1_INTR

56 - will be cancelled

TIMER2_INTR

57 - will be cancelled

TG0_T0_EDGE_INTR

58 - interrupt of TIMER_GROUP0, TIMER0, EDGE

TG0_T1_EDGE_INTR

59 - interrupt of TIMER_GROUP0, TIMER1, EDGE

TG0_WDT_EDGE_INTR

60 - interrupt of TIMER_GROUP0, WATCH DOG, EDGE

TG0_LACT_EDGE_INTR

61 - interrupt of TIMER_GROUP0, LACT, EDGE

TG1_T0_EDGE_INTR

62 - interrupt of TIMER_GROUP1, TIMER0, EDGE

TG1_T1_EDGE_INTR

63 - interrupt of TIMER_GROUP1, TIMER1, EDGE

TG1_WDT_EDGE_INTR

64 - interrupt of TIMER_GROUP1, WATCHDOG, EDGE

TG1_LACT_EDGE_INTR

65 - interrupt of TIMER_GROUP0, LACT, EDGE

MMU_IA_INTR

66 - interrupt of MMU Invalid Access, LEVEL

MPU_IA_INTR

67 - interrupt of MPU Invalid Access, LEVEL

CACHE_IA_INTR

68 - interrupt of Cache Invalid Access, LEVEL

INTERNAL_TIMER0_INTR

69 - Internal Timer 0 interrupt

INTERNAL_SOFTWARE_LEVEL_1_INTR

70 - Software Level 1 interrupt

INTERNAL_PROFILING_INTR

71 - Profiling interrupt

INTERNAL_TIMER1_INTR

72 - Internal Timer 1 interrupt

INTERNAL_TIMER2_INTR

73 - Internal Timer 1 interrupt

INTERNAL_SOFTWARE_LEVEL_3_INTR

74 - Software Level 3 interrupt

Implementations

impl Interrupt

pub fn try_from(value: u8) -> Result<Self, TryFromInterruptError>

Trait Implementations

impl Clone for Interrupt

fn clone(&self) -> Interrupt

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for Interrupt

impl Debug for Interrupt

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Eq for Interrupt

impl Nr for Interrupt

fn nr(&self) -> u8

Returns the number associated with an interrupt

impl PartialEq<Interrupt> for Interrupt

fn eq(&self, other: &Interrupt) -> bool

This method tests for self and other values to be equal, and is used by ==.

#[must_use]fn ne(&self, other: &Rhs) -> bool

This method tests for !=.

impl StructuralEq for Interrupt

impl StructuralPartialEq for Interrupt