Files
esp32
aes
apb_ctrl
dport
access_check.rsahb_lite_mask.rsahb_mpu_table_0.rsahb_mpu_table_1.rsahblite_mpu_table_apb_ctrl.rsahblite_mpu_table_bb.rsahblite_mpu_table_bt.rsahblite_mpu_table_bt_buffer.rsahblite_mpu_table_btmac.rsahblite_mpu_table_can.rsahblite_mpu_table_efuse.rsahblite_mpu_table_emac.rsahblite_mpu_table_fe.rsahblite_mpu_table_fe2.rsahblite_mpu_table_gpio.rsahblite_mpu_table_hinf.rsahblite_mpu_table_i2c.rsahblite_mpu_table_i2c_ext0.rsahblite_mpu_table_i2c_ext1.rsahblite_mpu_table_i2s0.rsahblite_mpu_table_i2s1.rsahblite_mpu_table_io_mux.rsahblite_mpu_table_ledc.rsahblite_mpu_table_misc.rsahblite_mpu_table_pcnt.rsahblite_mpu_table_pwm0.rsahblite_mpu_table_pwm1.rsahblite_mpu_table_pwm2.rsahblite_mpu_table_pwm3.rsahblite_mpu_table_pwr.rsahblite_mpu_table_rmt.rsahblite_mpu_table_rtc.rsahblite_mpu_table_rwbt.rsahblite_mpu_table_sdio_host.rsahblite_mpu_table_slc.rsahblite_mpu_table_slchost.rsahblite_mpu_table_spi0.rsahblite_mpu_table_spi1.rsahblite_mpu_table_spi2.rsahblite_mpu_table_spi3.rsahblite_mpu_table_spi_encrypt.rsahblite_mpu_table_timer.rsahblite_mpu_table_timergroup.rsahblite_mpu_table_timergroup1.rsahblite_mpu_table_uart.rsahblite_mpu_table_uart1.rsahblite_mpu_table_uart2.rsahblite_mpu_table_uhci0.rsahblite_mpu_table_uhci1.rsahblite_mpu_table_wdg.rsahblite_mpu_table_wifimac.rsapp_bb_int_map.rsapp_boot_remap_ctrl.rsapp_bt_bb_int_map.rsapp_bt_bb_nmi_map.rsapp_bt_mac_int_map.rsapp_cache_ctrl.rsapp_cache_ctrl1.rsapp_cache_ia_int_map.rsapp_cache_lock_0_addr.rsapp_cache_lock_1_addr.rsapp_cache_lock_2_addr.rsapp_cache_lock_3_addr.rsapp_can_int_map.rsapp_cpu_intr_from_cpu_0_map.rsapp_cpu_intr_from_cpu_1_map.rsapp_cpu_intr_from_cpu_2_map.rsapp_cpu_intr_from_cpu_3_map.rsapp_cpu_record_ctrl.rsapp_cpu_record_pdebugdata.rsapp_cpu_record_pdebuginst.rsapp_cpu_record_pdebugls0addr.rsapp_cpu_record_pdebugls0data.rsapp_cpu_record_pdebugls0stat.rsapp_cpu_record_pdebugpc.rsapp_cpu_record_pdebugstatus.rsapp_cpu_record_pid.rsapp_cpu_record_status.rsapp_dcache_dbug0.rsapp_dcache_dbug1.rsapp_dcache_dbug2.rsapp_dcache_dbug3.rsapp_dcache_dbug4.rsapp_dcache_dbug5.rsapp_dcache_dbug6.rsapp_dcache_dbug7.rsapp_dcache_dbug8.rsapp_dcache_dbug9.rsapp_dport_apb_mask0.rsapp_dport_apb_mask1.rsapp_efuse_int_map.rsapp_emac_int_map.rsapp_gpio_interrupt_map.rsapp_gpio_interrupt_nmi_map.rsapp_i2c_ext0_intr_map.rsapp_i2c_ext1_intr_map.rsapp_i2s0_int_map.rsapp_i2s1_int_map.rsapp_intr_status_0.rsapp_intr_status_1.rsapp_intr_status_2.rsapp_intrusion_ctrl.rsapp_intrusion_status.rsapp_ledc_int_map.rsapp_mac_intr_map.rsapp_mac_nmi_map.rsapp_mmu_ia_int_map.rsapp_mpu_ia_int_map.rsapp_pcnt_intr_map.rsapp_pwm0_intr_map.rsapp_pwm1_intr_map.rsapp_pwm2_intr_map.rsapp_pwm3_intr_map.rsapp_rmt_intr_map.rsapp_rsa_intr_map.rsapp_rtc_core_intr_map.rsapp_rwble_irq_map.rsapp_rwble_nmi_map.rsapp_rwbt_irq_map.rsapp_rwbt_nmi_map.rsapp_sdio_host_interrupt_map.rsapp_slc0_intr_map.rsapp_slc1_intr_map.rsapp_spi1_dma_int_map.rsapp_spi2_dma_int_map.rsapp_spi3_dma_int_map.rsapp_spi_intr_0_map.rsapp_spi_intr_1_map.rsapp_spi_intr_2_map.rsapp_spi_intr_3_map.rsapp_tg1_lact_edge_int_map.rsapp_tg1_lact_level_int_map.rsapp_tg1_t0_edge_int_map.rsapp_tg1_t0_level_int_map.rsapp_tg1_t1_edge_int_map.rsapp_tg1_t1_level_int_map.rsapp_tg1_wdt_edge_int_map.rsapp_tg1_wdt_level_int_map.rsapp_tg_lact_edge_int_map.rsapp_tg_lact_level_int_map.rsapp_tg_t0_edge_int_map.rsapp_tg_t0_level_int_map.rsapp_tg_t1_edge_int_map.rsapp_tg_t1_level_int_map.rsapp_tg_wdt_edge_int_map.rsapp_tg_wdt_level_int_map.rsapp_timer_int1_map.rsapp_timer_int2_map.rsapp_tracemem_ena.rsapp_uart1_intr_map.rsapp_uart2_intr_map.rsapp_uart_intr_map.rsapp_uhci0_intr_map.rsapp_uhci1_intr_map.rsapp_vecbase_ctrl.rsapp_vecbase_set.rsapp_wdg_int_map.rsappcpu_ctrl_a.rsappcpu_ctrl_b.rsappcpu_ctrl_c.rsappcpu_ctrl_d.rsbt_lpck_div_frac.rsbt_lpck_div_int.rscache_ia_int_en.rscache_mux_mode.rscore_rst_en.rscpu_intr_from_cpu_0.rscpu_intr_from_cpu_1.rscpu_intr_from_cpu_2.rscpu_intr_from_cpu_3.rscpu_per_conf.rsdate.rsdmmu_page_mode.rsdmmu_table0.rsdmmu_table1.rsdmmu_table10.rsdmmu_table11.rsdmmu_table12.rsdmmu_table13.rsdmmu_table14.rsdmmu_table15.rsdmmu_table2.rsdmmu_table3.rsdmmu_table4.rsdmmu_table5.rsdmmu_table6.rsdmmu_table7.rsdmmu_table8.rsdmmu_table9.rsfront_end_mem_pd.rshost_inf_sel.rsimmu_page_mode.rsimmu_table0.rsimmu_table1.rsimmu_table10.rsimmu_table11.rsimmu_table12.rsimmu_table13.rsimmu_table14.rsimmu_table15.rsimmu_table2.rsimmu_table3.rsimmu_table4.rsimmu_table5.rsimmu_table6.rsimmu_table7.rsimmu_table8.rsimmu_table9.rsiram_dram_ahb_sel.rsmem_access_dbug0.rsmem_access_dbug1.rsmem_pd_mask.rsmmu_ia_int_en.rsmpu_ia_int_en.rsperi_clk_en.rsperi_rst_en.rsperip_clk_en.rsperip_rst_en.rspro_bb_int_map.rspro_boot_remap_ctrl.rspro_bt_bb_int_map.rspro_bt_bb_nmi_map.rspro_bt_mac_int_map.rspro_cache_ctrl.rspro_cache_ctrl1.rspro_cache_ia_int_map.rspro_cache_lock_0_addr.rspro_cache_lock_1_addr.rspro_cache_lock_2_addr.rspro_cache_lock_3_addr.rspro_can_int_map.rspro_cpu_intr_from_cpu_0_map.rspro_cpu_intr_from_cpu_1_map.rspro_cpu_intr_from_cpu_2_map.rspro_cpu_intr_from_cpu_3_map.rspro_cpu_record_ctrl.rspro_cpu_record_pdebugdata.rspro_cpu_record_pdebuginst.rspro_cpu_record_pdebugls0addr.rspro_cpu_record_pdebugls0data.rspro_cpu_record_pdebugls0stat.rspro_cpu_record_pdebugpc.rspro_cpu_record_pdebugstatus.rspro_cpu_record_pid.rspro_cpu_record_status.rspro_dcache_dbug0.rspro_dcache_dbug1.rspro_dcache_dbug2.rspro_dcache_dbug3.rspro_dcache_dbug4.rspro_dcache_dbug5.rspro_dcache_dbug6.rspro_dcache_dbug7.rspro_dcache_dbug8.rspro_dcache_dbug9.rspro_dport_apb_mask0.rspro_dport_apb_mask1.rspro_efuse_int_map.rspro_emac_int_map.rspro_gpio_interrupt_map.rspro_gpio_interrupt_nmi_map.rspro_i2c_ext0_intr_map.rspro_i2c_ext1_intr_map.rspro_i2s0_int_map.rspro_i2s1_int_map.rspro_intr_status_0.rspro_intr_status_1.rspro_intr_status_2.rspro_intrusion_ctrl.rspro_intrusion_status.rspro_ledc_int_map.rspro_mac_intr_map.rspro_mac_nmi_map.rspro_mmu_ia_int_map.rspro_mpu_ia_int_map.rspro_pcnt_intr_map.rspro_pwm0_intr_map.rspro_pwm1_intr_map.rspro_pwm2_intr_map.rspro_pwm3_intr_map.rspro_rmt_intr_map.rspro_rsa_intr_map.rspro_rtc_core_intr_map.rspro_rwble_irq_map.rspro_rwble_nmi_map.rspro_rwbt_irq_map.rspro_rwbt_nmi_map.rspro_sdio_host_interrupt_map.rspro_slc0_intr_map.rspro_slc1_intr_map.rspro_spi1_dma_int_map.rspro_spi2_dma_int_map.rspro_spi3_dma_int_map.rspro_spi_intr_0_map.rspro_spi_intr_1_map.rspro_spi_intr_2_map.rspro_spi_intr_3_map.rspro_tg1_lact_edge_int_map.rspro_tg1_lact_level_int_map.rspro_tg1_t0_edge_int_map.rspro_tg1_t0_level_int_map.rspro_tg1_t1_edge_int_map.rspro_tg1_t1_level_int_map.rspro_tg1_wdt_edge_int_map.rspro_tg1_wdt_level_int_map.rspro_tg_lact_edge_int_map.rspro_tg_lact_level_int_map.rspro_tg_t0_edge_int_map.rspro_tg_t0_level_int_map.rspro_tg_t1_edge_int_map.rspro_tg_t1_level_int_map.rspro_tg_wdt_edge_int_map.rspro_tg_wdt_level_int_map.rspro_timer_int1_map.rspro_timer_int2_map.rspro_tracemem_ena.rspro_uart1_intr_map.rspro_uart2_intr_map.rspro_uart_intr_map.rspro_uhci0_intr_map.rspro_uhci1_intr_map.rspro_vecbase_ctrl.rspro_vecbase_set.rspro_wdg_int_map.rsrom_fo_ctrl.rsrom_mpu_ena.rsrom_mpu_table0.rsrom_mpu_table1.rsrom_mpu_table2.rsrom_mpu_table3.rsrom_pd_ctrl.rsrsa_pd_ctrl.rssecure_boot_ctrl.rsshrom_mpu_table0.rsshrom_mpu_table1.rsshrom_mpu_table10.rsshrom_mpu_table11.rsshrom_mpu_table12.rsshrom_mpu_table13.rsshrom_mpu_table14.rsshrom_mpu_table15.rsshrom_mpu_table16.rsshrom_mpu_table17.rsshrom_mpu_table18.rsshrom_mpu_table19.rsshrom_mpu_table2.rsshrom_mpu_table20.rsshrom_mpu_table21.rsshrom_mpu_table22.rsshrom_mpu_table23.rsshrom_mpu_table3.rsshrom_mpu_table4.rsshrom_mpu_table5.rsshrom_mpu_table6.rsshrom_mpu_table7.rsshrom_mpu_table8.rsshrom_mpu_table9.rsspi_dma_chan_sel.rssram_fo_ctrl_0.rssram_fo_ctrl_1.rssram_pd_ctrl_0.rssram_pd_ctrl_1.rstag_fo_ctrl.rstracemem_mux_mode.rswifi_bb_cfg.rswifi_bb_cfg_2.rswifi_clk_en.rs
efuse
gpio
acpu_int.rsacpu_int1.rsacpu_nmi_int.rsacpu_nmi_int1.rsbt_select.rscali_conf.rscali_data.rscpusdio_int.rscpusdio_int1.rsenable.rsenable1.rsenable1_w1tc.rsenable1_w1ts.rsenable_w1tc.rsenable_w1ts.rsfunc0_in_sel_cfg.rsfunc0_out_sel_cfg.rsfunc100_in_sel_cfg.rsfunc101_in_sel_cfg.rsfunc102_in_sel_cfg.rsfunc103_in_sel_cfg.rsfunc104_in_sel_cfg.rsfunc105_in_sel_cfg.rsfunc106_in_sel_cfg.rsfunc107_in_sel_cfg.rsfunc108_in_sel_cfg.rsfunc109_in_sel_cfg.rsfunc10_in_sel_cfg.rsfunc10_out_sel_cfg.rsfunc110_in_sel_cfg.rsfunc111_in_sel_cfg.rsfunc112_in_sel_cfg.rsfunc113_in_sel_cfg.rsfunc114_in_sel_cfg.rsfunc115_in_sel_cfg.rsfunc116_in_sel_cfg.rsfunc117_in_sel_cfg.rsfunc118_in_sel_cfg.rsfunc119_in_sel_cfg.rsfunc11_in_sel_cfg.rsfunc11_out_sel_cfg.rsfunc120_in_sel_cfg.rsfunc121_in_sel_cfg.rsfunc122_in_sel_cfg.rsfunc123_in_sel_cfg.rsfunc124_in_sel_cfg.rsfunc125_in_sel_cfg.rsfunc126_in_sel_cfg.rsfunc127_in_sel_cfg.rsfunc128_in_sel_cfg.rsfunc129_in_sel_cfg.rsfunc12_in_sel_cfg.rsfunc12_out_sel_cfg.rsfunc130_in_sel_cfg.rsfunc131_in_sel_cfg.rsfunc132_in_sel_cfg.rsfunc133_in_sel_cfg.rsfunc134_in_sel_cfg.rsfunc135_in_sel_cfg.rsfunc136_in_sel_cfg.rsfunc137_in_sel_cfg.rsfunc138_in_sel_cfg.rsfunc139_in_sel_cfg.rsfunc13_in_sel_cfg.rsfunc13_out_sel_cfg.rsfunc140_in_sel_cfg.rsfunc141_in_sel_cfg.rsfunc142_in_sel_cfg.rsfunc143_in_sel_cfg.rsfunc144_in_sel_cfg.rsfunc145_in_sel_cfg.rsfunc146_in_sel_cfg.rsfunc147_in_sel_cfg.rsfunc148_in_sel_cfg.rsfunc149_in_sel_cfg.rsfunc14_in_sel_cfg.rsfunc14_out_sel_cfg.rsfunc150_in_sel_cfg.rsfunc151_in_sel_cfg.rsfunc152_in_sel_cfg.rsfunc153_in_sel_cfg.rsfunc154_in_sel_cfg.rsfunc155_in_sel_cfg.rsfunc156_in_sel_cfg.rsfunc157_in_sel_cfg.rsfunc158_in_sel_cfg.rsfunc159_in_sel_cfg.rsfunc15_in_sel_cfg.rsfunc15_out_sel_cfg.rsfunc160_in_sel_cfg.rsfunc161_in_sel_cfg.rsfunc162_in_sel_cfg.rsfunc163_in_sel_cfg.rsfunc164_in_sel_cfg.rsfunc165_in_sel_cfg.rsfunc166_in_sel_cfg.rsfunc167_in_sel_cfg.rsfunc168_in_sel_cfg.rsfunc169_in_sel_cfg.rsfunc16_in_sel_cfg.rsfunc16_out_sel_cfg.rsfunc170_in_sel_cfg.rsfunc171_in_sel_cfg.rsfunc172_in_sel_cfg.rsfunc173_in_sel_cfg.rsfunc174_in_sel_cfg.rsfunc175_in_sel_cfg.rsfunc176_in_sel_cfg.rsfunc177_in_sel_cfg.rsfunc178_in_sel_cfg.rsfunc179_in_sel_cfg.rsfunc17_in_sel_cfg.rsfunc17_out_sel_cfg.rsfunc180_in_sel_cfg.rsfunc181_in_sel_cfg.rsfunc182_in_sel_cfg.rsfunc183_in_sel_cfg.rsfunc184_in_sel_cfg.rsfunc185_in_sel_cfg.rsfunc186_in_sel_cfg.rsfunc187_in_sel_cfg.rsfunc188_in_sel_cfg.rsfunc189_in_sel_cfg.rsfunc18_in_sel_cfg.rsfunc18_out_sel_cfg.rsfunc190_in_sel_cfg.rsfunc191_in_sel_cfg.rsfunc192_in_sel_cfg.rsfunc193_in_sel_cfg.rsfunc194_in_sel_cfg.rsfunc195_in_sel_cfg.rsfunc196_in_sel_cfg.rsfunc197_in_sel_cfg.rsfunc198_in_sel_cfg.rsfunc199_in_sel_cfg.rsfunc19_in_sel_cfg.rsfunc19_out_sel_cfg.rsfunc1_in_sel_cfg.rsfunc1_out_sel_cfg.rsfunc200_in_sel_cfg.rsfunc201_in_sel_cfg.rsfunc202_in_sel_cfg.rsfunc203_in_sel_cfg.rsfunc204_in_sel_cfg.rsfunc205_in_sel_cfg.rsfunc206_in_sel_cfg.rsfunc207_in_sel_cfg.rsfunc208_in_sel_cfg.rsfunc209_in_sel_cfg.rsfunc20_in_sel_cfg.rsfunc20_out_sel_cfg.rsfunc210_in_sel_cfg.rsfunc211_in_sel_cfg.rsfunc212_in_sel_cfg.rsfunc213_in_sel_cfg.rsfunc214_in_sel_cfg.rsfunc215_in_sel_cfg.rsfunc216_in_sel_cfg.rsfunc217_in_sel_cfg.rsfunc218_in_sel_cfg.rsfunc219_in_sel_cfg.rsfunc21_in_sel_cfg.rsfunc21_out_sel_cfg.rsfunc220_in_sel_cfg.rsfunc221_in_sel_cfg.rsfunc222_in_sel_cfg.rsfunc223_in_sel_cfg.rsfunc224_in_sel_cfg.rsfunc225_in_sel_cfg.rsfunc226_in_sel_cfg.rsfunc227_in_sel_cfg.rsfunc228_in_sel_cfg.rsfunc229_in_sel_cfg.rsfunc22_in_sel_cfg.rsfunc22_out_sel_cfg.rsfunc230_in_sel_cfg.rsfunc231_in_sel_cfg.rsfunc232_in_sel_cfg.rsfunc233_in_sel_cfg.rsfunc234_in_sel_cfg.rsfunc235_in_sel_cfg.rsfunc236_in_sel_cfg.rsfunc237_in_sel_cfg.rsfunc238_in_sel_cfg.rsfunc239_in_sel_cfg.rsfunc23_in_sel_cfg.rsfunc23_out_sel_cfg.rsfunc240_in_sel_cfg.rsfunc241_in_sel_cfg.rsfunc242_in_sel_cfg.rsfunc243_in_sel_cfg.rsfunc244_in_sel_cfg.rsfunc245_in_sel_cfg.rsfunc246_in_sel_cfg.rsfunc247_in_sel_cfg.rsfunc248_in_sel_cfg.rsfunc249_in_sel_cfg.rsfunc24_in_sel_cfg.rsfunc24_out_sel_cfg.rsfunc250_in_sel_cfg.rsfunc251_in_sel_cfg.rsfunc252_in_sel_cfg.rsfunc253_in_sel_cfg.rsfunc254_in_sel_cfg.rsfunc255_in_sel_cfg.rsfunc25_in_sel_cfg.rsfunc25_out_sel_cfg.rsfunc26_in_sel_cfg.rsfunc26_out_sel_cfg.rsfunc27_in_sel_cfg.rsfunc27_out_sel_cfg.rsfunc28_in_sel_cfg.rsfunc28_out_sel_cfg.rsfunc29_in_sel_cfg.rsfunc29_out_sel_cfg.rsfunc2_in_sel_cfg.rsfunc2_out_sel_cfg.rsfunc30_in_sel_cfg.rsfunc30_out_sel_cfg.rsfunc31_in_sel_cfg.rsfunc31_out_sel_cfg.rsfunc32_in_sel_cfg.rsfunc32_out_sel_cfg.rsfunc33_in_sel_cfg.rsfunc33_out_sel_cfg.rsfunc34_in_sel_cfg.rsfunc34_out_sel_cfg.rsfunc35_in_sel_cfg.rsfunc35_out_sel_cfg.rsfunc36_in_sel_cfg.rsfunc36_out_sel_cfg.rsfunc37_in_sel_cfg.rsfunc37_out_sel_cfg.rsfunc38_in_sel_cfg.rsfunc38_out_sel_cfg.rsfunc39_in_sel_cfg.rsfunc39_out_sel_cfg.rsfunc3_in_sel_cfg.rsfunc3_out_sel_cfg.rsfunc40_in_sel_cfg.rsfunc41_in_sel_cfg.rsfunc42_in_sel_cfg.rsfunc43_in_sel_cfg.rsfunc44_in_sel_cfg.rsfunc45_in_sel_cfg.rsfunc46_in_sel_cfg.rsfunc47_in_sel_cfg.rsfunc48_in_sel_cfg.rsfunc49_in_sel_cfg.rsfunc4_in_sel_cfg.rsfunc4_out_sel_cfg.rsfunc50_in_sel_cfg.rsfunc51_in_sel_cfg.rsfunc52_in_sel_cfg.rsfunc53_in_sel_cfg.rsfunc54_in_sel_cfg.rsfunc55_in_sel_cfg.rsfunc56_in_sel_cfg.rsfunc57_in_sel_cfg.rsfunc58_in_sel_cfg.rsfunc59_in_sel_cfg.rsfunc5_in_sel_cfg.rsfunc5_out_sel_cfg.rsfunc60_in_sel_cfg.rsfunc61_in_sel_cfg.rsfunc62_in_sel_cfg.rsfunc63_in_sel_cfg.rsfunc64_in_sel_cfg.rsfunc65_in_sel_cfg.rsfunc66_in_sel_cfg.rsfunc67_in_sel_cfg.rsfunc68_in_sel_cfg.rsfunc69_in_sel_cfg.rsfunc6_in_sel_cfg.rsfunc6_out_sel_cfg.rsfunc70_in_sel_cfg.rsfunc71_in_sel_cfg.rsfunc72_in_sel_cfg.rsfunc73_in_sel_cfg.rsfunc74_in_sel_cfg.rsfunc75_in_sel_cfg.rsfunc76_in_sel_cfg.rsfunc77_in_sel_cfg.rsfunc78_in_sel_cfg.rsfunc79_in_sel_cfg.rsfunc7_in_sel_cfg.rsfunc7_out_sel_cfg.rsfunc80_in_sel_cfg.rsfunc81_in_sel_cfg.rsfunc82_in_sel_cfg.rsfunc83_in_sel_cfg.rsfunc84_in_sel_cfg.rsfunc85_in_sel_cfg.rsfunc86_in_sel_cfg.rsfunc87_in_sel_cfg.rsfunc88_in_sel_cfg.rsfunc89_in_sel_cfg.rsfunc8_in_sel_cfg.rsfunc8_out_sel_cfg.rsfunc90_in_sel_cfg.rsfunc91_in_sel_cfg.rsfunc92_in_sel_cfg.rsfunc93_in_sel_cfg.rsfunc94_in_sel_cfg.rsfunc95_in_sel_cfg.rsfunc96_in_sel_cfg.rsfunc97_in_sel_cfg.rsfunc98_in_sel_cfg.rsfunc99_in_sel_cfg.rsfunc9_in_sel_cfg.rsfunc9_out_sel_cfg.rsin1.rsin_.rsout.rsout1.rsout1_w1tc.rsout1_w1ts.rsout_w1tc.rsout_w1ts.rspcpu_int.rspcpu_int1.rspcpu_nmi_int.rspcpu_nmi_int1.rspin0.rspin1.rspin10.rspin11.rspin12.rspin13.rspin14.rspin15.rspin16.rspin17.rspin18.rspin19.rspin2.rspin20.rspin21.rspin22.rspin23.rspin24.rspin25.rspin26.rspin27.rspin28.rspin29.rspin3.rspin30.rspin31.rspin32.rspin33.rspin34.rspin35.rspin36.rspin37.rspin38.rspin39.rspin4.rspin5.rspin6.rspin7.rspin8.rspin9.rssdio_select.rsstatus.rsstatus1.rsstatus1_w1tc.rsstatus1_w1ts.rsstatus_w1tc.rsstatus_w1ts.rsstrap.rs
gpio_sd
hinf
i2c
i2s
io_mux
ledc
mcpwm
pcnt
rmt
rtc_i2c
rtccntl
rtcio
sens
slc
slchost
host_slc0_host_pf.rshost_slc0host_func1_int_ena.rshost_slc0host_func2_int_ena.rshost_slc0host_int_clr.rshost_slc0host_int_ena.rshost_slc0host_int_ena1.rshost_slc0host_int_raw.rshost_slc0host_int_st.rshost_slc0host_len_wd.rshost_slc0host_rx_infor.rshost_slc0host_token_rdata.rshost_slc0host_token_wdata.rshost_slc1_host_pf.rshost_slc1host_func1_int_ena.rshost_slc1host_func2_int_ena.rshost_slc1host_int_clr.rshost_slc1host_int_ena.rshost_slc1host_int_ena1.rshost_slc1host_int_raw.rshost_slc1host_int_st.rshost_slc1host_rx_infor.rshost_slc1host_token_rdata.rshost_slc1host_token_wdata.rshost_slc_apbwin_conf.rshost_slc_apbwin_rdata.rshost_slc_apbwin_wdata.rshost_slchost_check_sum0.rshost_slchost_check_sum1.rshost_slchost_conf.rshost_slchost_conf_w0.rshost_slchost_conf_w1.rshost_slchost_conf_w10.rshost_slchost_conf_w11.rshost_slchost_conf_w12.rshost_slchost_conf_w13.rshost_slchost_conf_w14.rshost_slchost_conf_w15.rshost_slchost_conf_w2.rshost_slchost_conf_w3.rshost_slchost_conf_w4.rshost_slchost_conf_w5.rshost_slchost_conf_w6.rshost_slchost_conf_w7.rshost_slchost_conf_w8.rshost_slchost_conf_w9.rshost_slchost_func2_0.rshost_slchost_func2_1.rshost_slchost_func2_2.rshost_slchost_gpio_in0.rshost_slchost_gpio_in1.rshost_slchost_gpio_status0.rshost_slchost_gpio_status1.rshost_slchost_inf_st.rshost_slchost_pkt_len.rshost_slchost_pkt_len0.rshost_slchost_pkt_len1.rshost_slchost_pkt_len2.rshost_slchost_rdclr0.rshost_slchost_rdclr1.rshost_slchost_state_w0.rshost_slchost_state_w1.rshost_slchost_token_con.rshost_slchostdate.rshost_slchostid.rs
spi
syscon
timg
uart
uhci
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#[doc = "Reader of register CACHE_FCTRL"]
pub type R = crate::R<u32, super::CACHE_FCTRL>;
#[doc = "Writer for register CACHE_FCTRL"]
pub type W = crate::W<u32, super::CACHE_FCTRL>;
#[doc = "Register CACHE_FCTRL `reset()`'s with value 0"]
impl crate::ResetValue for super::CACHE_FCTRL {
    #[inline(always)]
    fn reset_value() -> Self::Ux {
        0
    }
}
#[doc = "Reader of field `CACHE_FLASH_PES_EN`"]
pub type CACHE_FLASH_PES_EN_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `CACHE_FLASH_PES_EN`"]
pub struct CACHE_FLASH_PES_EN_W<'a> {
    w: &'a mut W,
}
impl<'a> CACHE_FLASH_PES_EN_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
        self.w
    }
}
#[doc = "Reader of field `CACHE_FLASH_USR_CMD`"]
pub type CACHE_FLASH_USR_CMD_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `CACHE_FLASH_USR_CMD`"]
pub struct CACHE_FLASH_USR_CMD_W<'a> {
    w: &'a mut W,
}
impl<'a> CACHE_FLASH_USR_CMD_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
        self.w
    }
}
#[doc = "Reader of field `CACHE_USR_CMD_4BYTE`"]
pub type CACHE_USR_CMD_4BYTE_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `CACHE_USR_CMD_4BYTE`"]
pub struct CACHE_USR_CMD_4BYTE_W<'a> {
    w: &'a mut W,
}
impl<'a> CACHE_USR_CMD_4BYTE_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
        self.w
    }
}
#[doc = "Reader of field `CACHE_REQ_EN`"]
pub type CACHE_REQ_EN_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `CACHE_REQ_EN`"]
pub struct CACHE_REQ_EN_W<'a> {
    w: &'a mut W,
}
impl<'a> CACHE_REQ_EN_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
        self.w
    }
}
impl R {
    #[doc = "Bit 3"]
    #[inline(always)]
    pub fn cache_flash_pes_en(&self) -> CACHE_FLASH_PES_EN_R {
        CACHE_FLASH_PES_EN_R::new(((self.bits >> 3) & 0x01) != 0)
    }
    #[doc = "Bit 2"]
    #[inline(always)]
    pub fn cache_flash_usr_cmd(&self) -> CACHE_FLASH_USR_CMD_R {
        CACHE_FLASH_USR_CMD_R::new(((self.bits >> 2) & 0x01) != 0)
    }
    #[doc = "Bit 1"]
    #[inline(always)]
    pub fn cache_usr_cmd_4byte(&self) -> CACHE_USR_CMD_4BYTE_R {
        CACHE_USR_CMD_4BYTE_R::new(((self.bits >> 1) & 0x01) != 0)
    }
    #[doc = "Bit 0"]
    #[inline(always)]
    pub fn cache_req_en(&self) -> CACHE_REQ_EN_R {
        CACHE_REQ_EN_R::new((self.bits & 0x01) != 0)
    }
}
impl W {
    #[doc = "Bit 3"]
    #[inline(always)]
    pub fn cache_flash_pes_en(&mut self) -> CACHE_FLASH_PES_EN_W {
        CACHE_FLASH_PES_EN_W { w: self }
    }
    #[doc = "Bit 2"]
    #[inline(always)]
    pub fn cache_flash_usr_cmd(&mut self) -> CACHE_FLASH_USR_CMD_W {
        CACHE_FLASH_USR_CMD_W { w: self }
    }
    #[doc = "Bit 1"]
    #[inline(always)]
    pub fn cache_usr_cmd_4byte(&mut self) -> CACHE_USR_CMD_4BYTE_W {
        CACHE_USR_CMD_4BYTE_W { w: self }
    }
    #[doc = "Bit 0"]
    #[inline(always)]
    pub fn cache_req_en(&mut self) -> CACHE_REQ_EN_W {
        CACHE_REQ_EN_W { w: self }
    }
}