esp32 0.40.1

Peripheral access crate for the ESP32
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178

#[doc = "Register `APP_DCACHE_DBUG3` reader"]
pub type R = crate::R<APP_DCACHE_DBUG3_SPEC>;
#[doc = "Register `APP_DCACHE_DBUG3` writer"]
pub type W = crate::W<APP_DCACHE_DBUG3_SPEC>;
#[doc = "Field `APP_MMU_RDATA` reader - "]
pub type APP_MMU_RDATA_R = crate::FieldReader<u16>;
#[doc = "Field `APP_CPU_DISABLED_CACHE_IA` reader - "]
pub type APP_CPU_DISABLED_CACHE_IA_R = crate::FieldReader;
#[doc = "Field `APP_CPU_DISABLED_CACHE_IA_OPPOSITE` reader - "]
pub type APP_CPU_DISABLED_CACHE_IA_OPPOSITE_R = crate::BitReader;
#[doc = "Field `APP_CPU_DISABLED_CACHE_IA_OPPOSITE` writer - "]
pub type APP_CPU_DISABLED_CACHE_IA_OPPOSITE_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APP_CPU_DISABLED_CACHE_IA_DRAM1` reader - "]
pub type APP_CPU_DISABLED_CACHE_IA_DRAM1_R = crate::BitReader;
#[doc = "Field `APP_CPU_DISABLED_CACHE_IA_DRAM1` writer - "]
pub type APP_CPU_DISABLED_CACHE_IA_DRAM1_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APP_CPU_DISABLED_CACHE_IA_IROM0` reader - "]
pub type APP_CPU_DISABLED_CACHE_IA_IROM0_R = crate::BitReader;
#[doc = "Field `APP_CPU_DISABLED_CACHE_IA_IROM0` writer - "]
pub type APP_CPU_DISABLED_CACHE_IA_IROM0_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APP_CPU_DISABLED_CACHE_IA_IRAM1` reader - "]
pub type APP_CPU_DISABLED_CACHE_IA_IRAM1_R = crate::BitReader;
#[doc = "Field `APP_CPU_DISABLED_CACHE_IA_IRAM1` writer - "]
pub type APP_CPU_DISABLED_CACHE_IA_IRAM1_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APP_CPU_DISABLED_CACHE_IA_IRAM0` reader - "]
pub type APP_CPU_DISABLED_CACHE_IA_IRAM0_R = crate::BitReader;
#[doc = "Field `APP_CPU_DISABLED_CACHE_IA_IRAM0` writer - "]
pub type APP_CPU_DISABLED_CACHE_IA_IRAM0_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APP_CPU_DISABLED_CACHE_IA_DROM0` reader - "]
pub type APP_CPU_DISABLED_CACHE_IA_DROM0_R = crate::BitReader;
#[doc = "Field `APP_CPU_DISABLED_CACHE_IA_DROM0` writer - "]
pub type APP_CPU_DISABLED_CACHE_IA_DROM0_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APP_CACHE_IRAM0_PID_ERROR` reader - "]
pub type APP_CACHE_IRAM0_PID_ERROR_R = crate::BitReader;
impl R {
    #[doc = "Bits 0:8"]
    #[inline(always)]
    pub fn app_mmu_rdata(&self) -> APP_MMU_RDATA_R {
        APP_MMU_RDATA_R::new((self.bits & 0x01ff) as u16)
    }
    #[doc = "Bits 9:14"]
    #[inline(always)]
    pub fn app_cpu_disabled_cache_ia(&self) -> APP_CPU_DISABLED_CACHE_IA_R {
        APP_CPU_DISABLED_CACHE_IA_R::new(((self.bits >> 9) & 0x3f) as u8)
    }
    #[doc = "Bit 9"]
    #[inline(always)]
    pub fn app_cpu_disabled_cache_ia_opposite(&self) -> APP_CPU_DISABLED_CACHE_IA_OPPOSITE_R {
        APP_CPU_DISABLED_CACHE_IA_OPPOSITE_R::new(((self.bits >> 9) & 1) != 0)
    }
    #[doc = "Bit 10"]
    #[inline(always)]
    pub fn app_cpu_disabled_cache_ia_dram1(&self) -> APP_CPU_DISABLED_CACHE_IA_DRAM1_R {
        APP_CPU_DISABLED_CACHE_IA_DRAM1_R::new(((self.bits >> 10) & 1) != 0)
    }
    #[doc = "Bit 11"]
    #[inline(always)]
    pub fn app_cpu_disabled_cache_ia_irom0(&self) -> APP_CPU_DISABLED_CACHE_IA_IROM0_R {
        APP_CPU_DISABLED_CACHE_IA_IROM0_R::new(((self.bits >> 11) & 1) != 0)
    }
    #[doc = "Bit 12"]
    #[inline(always)]
    pub fn app_cpu_disabled_cache_ia_iram1(&self) -> APP_CPU_DISABLED_CACHE_IA_IRAM1_R {
        APP_CPU_DISABLED_CACHE_IA_IRAM1_R::new(((self.bits >> 12) & 1) != 0)
    }
    #[doc = "Bit 13"]
    #[inline(always)]
    pub fn app_cpu_disabled_cache_ia_iram0(&self) -> APP_CPU_DISABLED_CACHE_IA_IRAM0_R {
        APP_CPU_DISABLED_CACHE_IA_IRAM0_R::new(((self.bits >> 13) & 1) != 0)
    }
    #[doc = "Bit 14"]
    #[inline(always)]
    pub fn app_cpu_disabled_cache_ia_drom0(&self) -> APP_CPU_DISABLED_CACHE_IA_DROM0_R {
        APP_CPU_DISABLED_CACHE_IA_DROM0_R::new(((self.bits >> 14) & 1) != 0)
    }
    #[doc = "Bit 15"]
    #[inline(always)]
    pub fn app_cache_iram0_pid_error(&self) -> APP_CACHE_IRAM0_PID_ERROR_R {
        APP_CACHE_IRAM0_PID_ERROR_R::new(((self.bits >> 15) & 1) != 0)
    }
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("APP_DCACHE_DBUG3")
            .field("app_mmu_rdata", &self.app_mmu_rdata())
            .field(
                "app_cpu_disabled_cache_ia",
                &self.app_cpu_disabled_cache_ia(),
            )
            .field(
                "app_cpu_disabled_cache_ia_opposite",
                &self.app_cpu_disabled_cache_ia_opposite(),
            )
            .field(
                "app_cpu_disabled_cache_ia_dram1",
                &self.app_cpu_disabled_cache_ia_dram1(),
            )
            .field(
                "app_cpu_disabled_cache_ia_irom0",
                &self.app_cpu_disabled_cache_ia_irom0(),
            )
            .field(
                "app_cpu_disabled_cache_ia_iram1",
                &self.app_cpu_disabled_cache_ia_iram1(),
            )
            .field(
                "app_cpu_disabled_cache_ia_iram0",
                &self.app_cpu_disabled_cache_ia_iram0(),
            )
            .field(
                "app_cpu_disabled_cache_ia_drom0",
                &self.app_cpu_disabled_cache_ia_drom0(),
            )
            .field(
                "app_cache_iram0_pid_error",
                &self.app_cache_iram0_pid_error(),
            )
            .finish()
    }
}
impl W {
    #[doc = "Bit 9"]
    #[inline(always)]
    pub fn app_cpu_disabled_cache_ia_opposite(
        &mut self,
    ) -> APP_CPU_DISABLED_CACHE_IA_OPPOSITE_W<'_, APP_DCACHE_DBUG3_SPEC> {
        APP_CPU_DISABLED_CACHE_IA_OPPOSITE_W::new(self, 9)
    }
    #[doc = "Bit 10"]
    #[inline(always)]
    pub fn app_cpu_disabled_cache_ia_dram1(
        &mut self,
    ) -> APP_CPU_DISABLED_CACHE_IA_DRAM1_W<'_, APP_DCACHE_DBUG3_SPEC> {
        APP_CPU_DISABLED_CACHE_IA_DRAM1_W::new(self, 10)
    }
    #[doc = "Bit 11"]
    #[inline(always)]
    pub fn app_cpu_disabled_cache_ia_irom0(
        &mut self,
    ) -> APP_CPU_DISABLED_CACHE_IA_IROM0_W<'_, APP_DCACHE_DBUG3_SPEC> {
        APP_CPU_DISABLED_CACHE_IA_IROM0_W::new(self, 11)
    }
    #[doc = "Bit 12"]
    #[inline(always)]
    pub fn app_cpu_disabled_cache_ia_iram1(
        &mut self,
    ) -> APP_CPU_DISABLED_CACHE_IA_IRAM1_W<'_, APP_DCACHE_DBUG3_SPEC> {
        APP_CPU_DISABLED_CACHE_IA_IRAM1_W::new(self, 12)
    }
    #[doc = "Bit 13"]
    #[inline(always)]
    pub fn app_cpu_disabled_cache_ia_iram0(
        &mut self,
    ) -> APP_CPU_DISABLED_CACHE_IA_IRAM0_W<'_, APP_DCACHE_DBUG3_SPEC> {
        APP_CPU_DISABLED_CACHE_IA_IRAM0_W::new(self, 13)
    }
    #[doc = "Bit 14"]
    #[inline(always)]
    pub fn app_cpu_disabled_cache_ia_drom0(
        &mut self,
    ) -> APP_CPU_DISABLED_CACHE_IA_DROM0_W<'_, APP_DCACHE_DBUG3_SPEC> {
        APP_CPU_DISABLED_CACHE_IA_DROM0_W::new(self, 14)
    }
}
#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`app_dcache_dbug3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_dcache_dbug3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct APP_DCACHE_DBUG3_SPEC;
impl crate::RegisterSpec for APP_DCACHE_DBUG3_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [`app_dcache_dbug3::R`](R) reader structure"]
impl crate::Readable for APP_DCACHE_DBUG3_SPEC {}
#[doc = "`write(|w| ..)` method takes [`app_dcache_dbug3::W`](W) writer structure"]
impl crate::Writable for APP_DCACHE_DBUG3_SPEC {
    type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets APP_DCACHE_DBUG3 to value 0"]
impl crate::Resettable for APP_DCACHE_DBUG3_SPEC {}