esp32 0.40.0

Peripheral access crate for the ESP32
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73

#[doc = "Register `EX_CLKOUT_CONF` reader"]
pub type R = crate::R<EX_CLKOUT_CONF_SPEC>;
#[doc = "Register `EX_CLKOUT_CONF` writer"]
pub type W = crate::W<EX_CLKOUT_CONF_SPEC>;
#[doc = "Field `DIV_NUM` reader - "]
pub type DIV_NUM_R = crate::FieldReader;
#[doc = "Field `DIV_NUM` writer - "]
pub type DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `H_DIV_NUM` reader - "]
pub type H_DIV_NUM_R = crate::FieldReader;
#[doc = "Field `H_DIV_NUM` writer - "]
pub type H_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `DLY_NUM` reader - "]
pub type DLY_NUM_R = crate::FieldReader;
#[doc = "Field `DLY_NUM` writer - "]
pub type DLY_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
impl R {
    #[doc = "Bits 0:3"]
    #[inline(always)]
    pub fn div_num(&self) -> DIV_NUM_R {
        DIV_NUM_R::new((self.bits & 0x0f) as u8)
    }
    #[doc = "Bits 4:7"]
    #[inline(always)]
    pub fn h_div_num(&self) -> H_DIV_NUM_R {
        H_DIV_NUM_R::new(((self.bits >> 4) & 0x0f) as u8)
    }
    #[doc = "Bits 8:9"]
    #[inline(always)]
    pub fn dly_num(&self) -> DLY_NUM_R {
        DLY_NUM_R::new(((self.bits >> 8) & 3) as u8)
    }
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("EX_CLKOUT_CONF")
            .field("div_num", &self.div_num())
            .field("h_div_num", &self.h_div_num())
            .field("dly_num", &self.dly_num())
            .finish()
    }
}
impl W {
    #[doc = "Bits 0:3"]
    #[inline(always)]
    pub fn div_num(&mut self) -> DIV_NUM_W<'_, EX_CLKOUT_CONF_SPEC> {
        DIV_NUM_W::new(self, 0)
    }
    #[doc = "Bits 4:7"]
    #[inline(always)]
    pub fn h_div_num(&mut self) -> H_DIV_NUM_W<'_, EX_CLKOUT_CONF_SPEC> {
        H_DIV_NUM_W::new(self, 4)
    }
    #[doc = "Bits 8:9"]
    #[inline(always)]
    pub fn dly_num(&mut self) -> DLY_NUM_W<'_, EX_CLKOUT_CONF_SPEC> {
        DLY_NUM_W::new(self, 8)
    }
}
#[doc = "RMII clock divider setting\n\nYou can [`read`](crate::Reg::read) this register and get [`ex_clkout_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ex_clkout_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EX_CLKOUT_CONF_SPEC;
impl crate::RegisterSpec for EX_CLKOUT_CONF_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [`ex_clkout_conf::R`](R) reader structure"]
impl crate::Readable for EX_CLKOUT_CONF_SPEC {}
#[doc = "`write(|w| ..)` method takes [`ex_clkout_conf::W`](W) writer structure"]
impl crate::Writable for EX_CLKOUT_CONF_SPEC {
    type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets EX_CLKOUT_CONF to value 0"]
impl crate::Resettable for EX_CLKOUT_CONF_SPEC {}