#[doc = "Reader of register CPU_PER_CONF"]
pub type R = crate::R<u32, super::CPU_PER_CONF>;
#[doc = "Writer for register CPU_PER_CONF"]
pub type W = crate::W<u32, super::CPU_PER_CONF>;
#[doc = "Register CPU_PER_CONF `reset()`'s with value 0"]
impl crate::ResetValue for super::CPU_PER_CONF {
type Type = u32;
#[inline(always)]
fn reset_value() -> Self::Type {
0
}
}
#[doc = "Reader of field `FAST_CLK_RTC_SEL`"]
pub type FAST_CLK_RTC_SEL_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `FAST_CLK_RTC_SEL`"]
pub struct FAST_CLK_RTC_SEL_W<'a> {
w: &'a mut W,
}
impl<'a> FAST_CLK_RTC_SEL_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
self.w
}
}
#[doc = "Reader of field `LOWSPEED_CLK_SEL`"]
pub type LOWSPEED_CLK_SEL_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `LOWSPEED_CLK_SEL`"]
pub struct LOWSPEED_CLK_SEL_W<'a> {
w: &'a mut W,
}
impl<'a> LOWSPEED_CLK_SEL_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
self.w
}
}
#[doc = "\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum CPUPERIOD_SEL_A {
#[doc = "0: Select 80 MHz clock"]
SEL_80 = 0,
#[doc = "1: Select 160 MHz clock"]
SEL_160 = 1,
#[doc = "2: Select 240 MHz clock"]
SEL_240 = 2,
}
impl From<CPUPERIOD_SEL_A> for u8 {
#[inline(always)]
fn from(variant: CPUPERIOD_SEL_A) -> Self {
variant as _
}
}
#[doc = "Reader of field `CPUPERIOD_SEL`"]
pub type CPUPERIOD_SEL_R = crate::R<u8, CPUPERIOD_SEL_A>;
impl CPUPERIOD_SEL_R {
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> crate::Variant<u8, CPUPERIOD_SEL_A> {
use crate::Variant::*;
match self.bits {
0 => Val(CPUPERIOD_SEL_A::SEL_80),
1 => Val(CPUPERIOD_SEL_A::SEL_160),
2 => Val(CPUPERIOD_SEL_A::SEL_240),
i => Res(i),
}
}
#[doc = "Checks if the value of the field is `SEL_80`"]
#[inline(always)]
pub fn is_sel_80(&self) -> bool {
*self == CPUPERIOD_SEL_A::SEL_80
}
#[doc = "Checks if the value of the field is `SEL_160`"]
#[inline(always)]
pub fn is_sel_160(&self) -> bool {
*self == CPUPERIOD_SEL_A::SEL_160
}
#[doc = "Checks if the value of the field is `SEL_240`"]
#[inline(always)]
pub fn is_sel_240(&self) -> bool {
*self == CPUPERIOD_SEL_A::SEL_240
}
}
#[doc = "Write proxy for field `CPUPERIOD_SEL`"]
pub struct CPUPERIOD_SEL_W<'a> {
w: &'a mut W,
}
impl<'a> CPUPERIOD_SEL_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: CPUPERIOD_SEL_A) -> &'a mut W {
unsafe { self.bits(variant.into()) }
}
#[doc = "Select 80 MHz clock"]
#[inline(always)]
pub fn sel_80(self) -> &'a mut W {
self.variant(CPUPERIOD_SEL_A::SEL_80)
}
#[doc = "Select 160 MHz clock"]
#[inline(always)]
pub fn sel_160(self) -> &'a mut W {
self.variant(CPUPERIOD_SEL_A::SEL_160)
}
#[doc = "Select 240 MHz clock"]
#[inline(always)]
pub fn sel_240(self) -> &'a mut W {
self.variant(CPUPERIOD_SEL_A::SEL_240)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
self.w
}
}
impl R {
#[doc = "Bit 3"]
#[inline(always)]
pub fn fast_clk_rtc_sel(&self) -> FAST_CLK_RTC_SEL_R {
FAST_CLK_RTC_SEL_R::new(((self.bits >> 3) & 0x01) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn lowspeed_clk_sel(&self) -> LOWSPEED_CLK_SEL_R {
LOWSPEED_CLK_SEL_R::new(((self.bits >> 2) & 0x01) != 0)
}
#[doc = "Bits 0:1"]
#[inline(always)]
pub fn cpuperiod_sel(&self) -> CPUPERIOD_SEL_R {
CPUPERIOD_SEL_R::new((self.bits & 0x03) as u8)
}
}
impl W {
#[doc = "Bit 3"]
#[inline(always)]
pub fn fast_clk_rtc_sel(&mut self) -> FAST_CLK_RTC_SEL_W {
FAST_CLK_RTC_SEL_W { w: self }
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn lowspeed_clk_sel(&mut self) -> LOWSPEED_CLK_SEL_W {
LOWSPEED_CLK_SEL_W { w: self }
}
#[doc = "Bits 0:1"]
#[inline(always)]
pub fn cpuperiod_sel(&mut self) -> CPUPERIOD_SEL_W {
CPUPERIOD_SEL_W { w: self }
}
}