Type Alias R

pub type R = R<CACHE_SCTRL_SPEC>;

Register CACHE_SCTRL reader

Aliased Type

struct R { /* private fields */ }

Implementations

impl R

pub fn usr_sram_dio(&self) -> USR_SRAM_DIO_R

Bit 1 - For SPI0 In the spi sram mode spi dual I/O mode enable 1: enable 0:disable

pub fn usr_sram_qio(&self) -> USR_SRAM_QIO_R

Bit 2 - For SPI0 In the spi sram mode spi quad I/O mode enable 1: enable 0:disable

pub fn usr_wr_sram_dummy(&self) -> USR_WR_SRAM_DUMMY_R

Bit 3 - For SPI0 In the spi sram mode it is the enable bit of dummy phase for write operations.

pub fn usr_rd_sram_dummy(&self) -> USR_RD_SRAM_DUMMY_R

Bit 4 - For SPI0 In the spi sram mode it is the enable bit of dummy phase for read operations.

pub fn cache_sram_usr_rcmd(&self) -> CACHE_SRAM_USR_RCMD_R

Bit 5 - For SPI0 In the spi sram mode cache read sram for user define command.

pub fn sram_bytes_len(&self) -> SRAM_BYTES_LEN_R

Bits 6:13 - For SPI0 In the sram mode it is the byte length of spi read sram data.

pub fn sram_dummy_cyclelen(&self) -> SRAM_DUMMY_CYCLELEN_R

Bits 14:21 - For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1).

pub fn sram_addr_bitlen(&self) -> SRAM_ADDR_BITLEN_R

Bits 22:27 - For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1).

pub fn cache_sram_usr_wcmd(&self) -> CACHE_SRAM_USR_WCMD_R

Bit 28 - For SPI0 In the spi sram mode cache write sram for user define command