[][src]Struct esp32::mcpwm::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub clk_cfg: CLK_CFG,
    pub timer0_cfg0: TIMER0_CFG0,
    pub timer0_cfg1: TIMER0_CFG1,
    pub timer0_sync: TIMER0_SYNC,
    pub timer0_status: TIMER0_STATUS,
    pub timer1_cfg0: TIMER1_CFG0,
    pub timer1_cfg1: TIMER1_CFG1,
    pub timer1_sync: TIMER1_SYNC,
    pub timer1_status: TIMER1_STATUS,
    pub timer2_cfg0: TIMER2_CFG0,
    pub timer2_cfg1: TIMER2_CFG1,
    pub timer2_sync: TIMER2_SYNC,
    pub timer2_status: TIMER2_STATUS,
    pub timer_synci_cfg: TIMER_SYNCI_CFG,
    pub operator_timersel: OPERATOR_TIMERSEL,
    pub gen0_stmp_cfg: GEN0_STMP_CFG,
    pub gen0_tstmp_a: GEN0_TSTMP_A,
    pub gen0_tstmp_b: GEN0_TSTMP_B,
    pub gen0_cfg0: GEN0_CFG0,
    pub gen0_force: GEN0_FORCE,
    pub gen0_a: GEN0_A,
    pub gen0_b: GEN0_B,
    pub dt0_cfg: DT0_CFG,
    pub dt0_fed_cfg: DT0_FED_CFG,
    pub dt0_red_cfg: DT0_RED_CFG,
    pub carrier0_cfg: CARRIER0_CFG,
    pub fh0_cfg0: FH0_CFG0,
    pub fh0_cfg1: FH0_CFG1,
    pub fh0_status: FH0_STATUS,
    pub gen1_stmp_cfg: GEN1_STMP_CFG,
    pub gen1_tstmp_a: GEN1_TSTMP_A,
    pub gen1_tstmp_b: GEN1_TSTMP_B,
    pub gen1_cfg0: GEN1_CFG0,
    pub gen1_force: GEN1_FORCE,
    pub gen1_a: GEN1_A,
    pub gen1_b: GEN1_B,
    pub dt1_cfg: DT1_CFG,
    pub dt1_fed_cfg: DT1_FED_CFG,
    pub dt1_red_cfg: DT1_RED_CFG,
    pub carrier1_cfg: CARRIER1_CFG,
    pub fh1_cfg0: FH1_CFG0,
    pub fh1_cfg1: FH1_CFG1,
    pub fh1_status: FH1_STATUS,
    pub gen2_stmp_cfg: GEN2_STMP_CFG,
    pub gen2_tstmp_a: GEN2_TSTMP_A,
    pub gen2_tstmp_b: GEN2_TSTMP_B,
    pub gen2_cfg0: GEN2_CFG0,
    pub gen2_force: GEN2_FORCE,
    pub gen2_a: GEN2_A,
    pub gen2_b: GEN2_B,
    pub dt2_cfg: DT2_CFG,
    pub dt2_fed_cfg: DT2_FED_CFG,
    pub dt2_red_cfg: DT2_RED_CFG,
    pub carrier2_cfg: CARRIER2_CFG,
    pub fh2_cfg0: FH2_CFG0,
    pub fh2_cfg1: FH2_CFG1,
    pub fh2_status: FH2_STATUS,
    pub fault_detect: FAULT_DETECT,
    pub cap_timer_cfg: CAP_TIMER_CFG,
    pub cap_timer_phase: CAP_TIMER_PHASE,
    pub cap_ch0_cfg: CAP_CH0_CFG,
    pub cap_ch1_cfg: CAP_CH1_CFG,
    pub cap_ch2_cfg: CAP_CH2_CFG,
    pub cap_ch0: CAP_CH0,
    pub cap_ch1: CAP_CH1,
    pub cap_ch2: CAP_CH2,
    pub cap_status: CAP_STATUS,
    pub update_cfg: UPDATE_CFG,
    pub mcmcpwm_int_ena_mcpwm: MCMCPWM_INT_ENA_MCPWM,
    pub mcmcpwm_int_raw_mcpwm: MCMCPWM_INT_RAW_MCPWM,
    pub mcmcpwm_int_st_mcpwm: MCMCPWM_INT_ST_MCPWM,
    pub mcmcpwm_int_clr_mcpwm: MCMCPWM_INT_CLR_MCPWM,
    pub clk: CLK,
    pub version: VERSION,
}

Register block

Fields

clk_cfg: CLK_CFG

0x00 - MCPWM_CLK_CFG

timer0_cfg0: TIMER0_CFG0

0x04 - MCPWM_TIMER0_CFG0

timer0_cfg1: TIMER0_CFG1

0x08 - MCPWM_TIMER0_CFG1

timer0_sync: TIMER0_SYNC

0x0c - MCPWM_TIMER0_SYNC

timer0_status: TIMER0_STATUS

0x10 - MCPWM_TIMER0_STATUS

timer1_cfg0: TIMER1_CFG0

0x14 - MCPWM_TIMER1_CFG0

timer1_cfg1: TIMER1_CFG1

0x18 - MCPWM_TIMER1_CFG1

timer1_sync: TIMER1_SYNC

0x1c - MCPWM_TIMER1_SYNC

timer1_status: TIMER1_STATUS

0x20 - MCPWM_TIMER1_STATUS

timer2_cfg0: TIMER2_CFG0

0x24 - MCPWM_TIMER2_CFG0

timer2_cfg1: TIMER2_CFG1

0x28 - MCPWM_TIMER2_CFG1

timer2_sync: TIMER2_SYNC

0x2c - MCPWM_TIMER2_SYNC

timer2_status: TIMER2_STATUS

0x30 - MCPWM_TIMER2_STATUS

timer_synci_cfg: TIMER_SYNCI_CFG

0x34 - MCPWM_TIMER_SYNCI_CFG

operator_timersel: OPERATOR_TIMERSEL

0x38 - MCPWM_OPERATOR_TIMERSEL

gen0_stmp_cfg: GEN0_STMP_CFG

0x3c - MCPWM_GEN0_STMP_CFG

gen0_tstmp_a: GEN0_TSTMP_A

0x40 - MCPWM_GEN0_TSTMP_A

gen0_tstmp_b: GEN0_TSTMP_B

0x44 - MCPWM_GEN0_TSTMP_B

gen0_cfg0: GEN0_CFG0

0x48 - MCPWM_GEN0_CFG0

gen0_force: GEN0_FORCE

0x4c - MCPWM_GEN0_FORCE

gen0_a: GEN0_A

0x50 - MCPWM_GEN0_A

gen0_b: GEN0_B

0x54 - MCPWM_GEN0_B

dt0_cfg: DT0_CFG

0x58 - MCPWM_DT0_CFG

dt0_fed_cfg: DT0_FED_CFG

0x5c - MCPWM_DT0_FED_CFG

dt0_red_cfg: DT0_RED_CFG

0x60 - MCPWM_DT0_RED_CFG

carrier0_cfg: CARRIER0_CFG

0x64 - MCPWM_CARRIER0_CFG

fh0_cfg0: FH0_CFG0

0x68 - MCPWM_FH0_CFG0

fh0_cfg1: FH0_CFG1

0x6c - MCPWM_FH0_CFG1

fh0_status: FH0_STATUS

0x70 - MCPWM_FH0_STATUS

gen1_stmp_cfg: GEN1_STMP_CFG

0x74 - MCPWM_GEN1_STMP_CFG

gen1_tstmp_a: GEN1_TSTMP_A

0x78 - MCPWM_GEN1_TSTMP_A

gen1_tstmp_b: GEN1_TSTMP_B

0x7c - MCPWM_GEN1_TSTMP_B

gen1_cfg0: GEN1_CFG0

0x80 - MCPWM_GEN1_CFG0

gen1_force: GEN1_FORCE

0x84 - MCPWM_GEN1_FORCE

gen1_a: GEN1_A

0x88 - MCPWM_GEN1_A

gen1_b: GEN1_B

0x8c - MCPWM_GEN1_B

dt1_cfg: DT1_CFG

0x90 - MCPWM_DT1_CFG

dt1_fed_cfg: DT1_FED_CFG

0x94 - MCPWM_DT1_FED_CFG

dt1_red_cfg: DT1_RED_CFG

0x98 - MCPWM_DT1_RED_CFG

carrier1_cfg: CARRIER1_CFG

0x9c - MCPWM_CARRIER1_CFG

fh1_cfg0: FH1_CFG0

0xa0 - MCPWM_FH1_CFG0

fh1_cfg1: FH1_CFG1

0xa4 - MCPWM_FH1_CFG1

fh1_status: FH1_STATUS

0xa8 - MCPWM_FH1_STATUS

gen2_stmp_cfg: GEN2_STMP_CFG

0xac - MCPWM_GEN2_STMP_CFG

gen2_tstmp_a: GEN2_TSTMP_A

0xb0 - MCPWM_GEN2_TSTMP_A

gen2_tstmp_b: GEN2_TSTMP_B

0xb4 - MCPWM_GEN2_TSTMP_B

gen2_cfg0: GEN2_CFG0

0xb8 - MCPWM_GEN2_CFG0

gen2_force: GEN2_FORCE

0xbc - MCPWM_GEN2_FORCE

gen2_a: GEN2_A

0xc0 - MCPWM_GEN2_A

gen2_b: GEN2_B

0xc4 - MCPWM_GEN2_B

dt2_cfg: DT2_CFG

0xc8 - MCPWM_DT2_CFG

dt2_fed_cfg: DT2_FED_CFG

0xcc - MCPWM_DT2_FED_CFG

dt2_red_cfg: DT2_RED_CFG

0xd0 - MCPWM_DT2_RED_CFG

carrier2_cfg: CARRIER2_CFG

0xd4 - MCPWM_CARRIER2_CFG

fh2_cfg0: FH2_CFG0

0xd8 - MCPWM_FH2_CFG0

fh2_cfg1: FH2_CFG1

0xdc - MCPWM_FH2_CFG1

fh2_status: FH2_STATUS

0xe0 - MCPWM_FH2_STATUS

fault_detect: FAULT_DETECT

0xe4 - MCPWM_FAULT_DETECT

cap_timer_cfg: CAP_TIMER_CFG

0xe8 - MCPWM_CAP_TIMER_CFG

cap_timer_phase: CAP_TIMER_PHASE

0xec - MCPWM_CAP_TIMER_PHASE

cap_ch0_cfg: CAP_CH0_CFG

0xf0 - MCPWM_CAP_CH0_CFG

cap_ch1_cfg: CAP_CH1_CFG

0xf4 - MCPWM_CAP_CH1_CFG

cap_ch2_cfg: CAP_CH2_CFG

0xf8 - MCPWM_CAP_CH2_CFG

cap_ch0: CAP_CH0

0xfc - MCPWM_CAP_CH0

cap_ch1: CAP_CH1

0x100 - MCPWM_CAP_CH1

cap_ch2: CAP_CH2

0x104 - MCPWM_CAP_CH2

cap_status: CAP_STATUS

0x108 - MCPWM_CAP_STATUS

update_cfg: UPDATE_CFG

0x10c - MCPWM_UPDATE_CFG

mcmcpwm_int_ena_mcpwm: MCMCPWM_INT_ENA_MCPWM

0x110 - MCMCPWM_INT_ENA_MCPWM

mcmcpwm_int_raw_mcpwm: MCMCPWM_INT_RAW_MCPWM

0x114 - MCMCPWM_INT_RAW_MCPWM

mcmcpwm_int_st_mcpwm: MCMCPWM_INT_ST_MCPWM

0x118 - MCMCPWM_INT_ST_MCPWM

mcmcpwm_int_clr_mcpwm: MCMCPWM_INT_CLR_MCPWM

0x11c - MCMCPWM_INT_CLR_MCPWM

clk: CLK

0x120 - MCPWM_CLK

version: VERSION

0x124 - MCPWM_VERSION

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