[−][src]Struct esp32::i2s::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub conf: CONF,
    pub int_raw: INT_RAW,
    pub int_st: INT_ST,
    pub int_ena: INT_ENA,
    pub int_clr: INT_CLR,
    pub timing: TIMING,
    pub fifo_conf: FIFO_CONF,
    pub rxeof_num: RXEOF_NUM,
    pub conf_sigle_data: CONF_SIGLE_DATA,
    pub conf_chan: CONF_CHAN,
    pub out_link: OUT_LINK,
    pub in_link: IN_LINK,
    pub out_eof_des_addr: OUT_EOF_DES_ADDR,
    pub in_eof_des_addr: IN_EOF_DES_ADDR,
    pub out_eof_bfr_des_addr: OUT_EOF_BFR_DES_ADDR,
    pub ahb_test: AHB_TEST,
    pub inlink_dscr: INLINK_DSCR,
    pub inlink_dscr_bf0: INLINK_DSCR_BF0,
    pub inlink_dscr_bf1: INLINK_DSCR_BF1,
    pub outlink_dscr: OUTLINK_DSCR,
    pub outlink_dscr_bf0: OUTLINK_DSCR_BF0,
    pub outlink_dscr_bf1: OUTLINK_DSCR_BF1,
    pub lc_conf: LC_CONF,
    pub outfifo_push: OUTFIFO_PUSH,
    pub infifo_pop: INFIFO_POP,
    pub lc_state0: LC_STATE0,
    pub lc_state1: LC_STATE1,
    pub lc_hung_conf: LC_HUNG_CONF,
    pub cvsd_conf0: CVSD_CONF0,
    pub cvsd_conf1: CVSD_CONF1,
    pub cvsd_conf2: CVSD_CONF2,
    pub plc_conf0: PLC_CONF0,
    pub plc_conf1: PLC_CONF1,
    pub plc_conf2: PLC_CONF2,
    pub esco_conf0: ESCO_CONF0,
    pub sco_conf0: SCO_CONF0,
    pub conf1: CONF1,
    pub pd_conf: PD_CONF,
    pub conf2: CONF2,
    pub clkm_conf: CLKM_CONF,
    pub sample_rate_conf: SAMPLE_RATE_CONF,
    pub pdm_conf: PDM_CONF,
    pub pdm_freq_conf: PDM_FREQ_CONF,
    pub state: STATE,
    pub date: DATE,
    // some fields omitted
}

Register block

Fields

conf: CONF

0x08 - I2S_CONF

int_raw: INT_RAW

0x0c - I2S_INT_RAW

int_st: INT_ST

0x10 - I2S_INT_ST

int_ena: INT_ENA

0x14 - I2S_INT_ENA

int_clr: INT_CLR

0x18 - I2S_INT_CLR

timing: TIMING

0x1c - I2S_TIMING

fifo_conf: FIFO_CONF

0x20 - I2S_FIFO_CONF

rxeof_num: RXEOF_NUM

0x24 - I2S_RXEOF_NUM

conf_sigle_data: CONF_SIGLE_DATA

0x28 - I2S_CONF_SIGLE_DATA

conf_chan: CONF_CHAN

0x2c - I2S_CONF_CHAN

out_link: OUT_LINK

0x30 - I2S_OUT_LINK

in_link: IN_LINK

0x34 - I2S_IN_LINK

out_eof_des_addr: OUT_EOF_DES_ADDR

0x38 - I2S_OUT_EOF_DES_ADDR

in_eof_des_addr: IN_EOF_DES_ADDR

0x3c - I2S_IN_EOF_DES_ADDR

out_eof_bfr_des_addr: OUT_EOF_BFR_DES_ADDR

0x40 - I2S_OUT_EOF_BFR_DES_ADDR

ahb_test: AHB_TEST

0x44 - I2S_AHB_TEST

inlink_dscr: INLINK_DSCR

0x48 - I2S_INLINK_DSCR

inlink_dscr_bf0: INLINK_DSCR_BF0

0x4c - I2S_INLINK_DSCR_BF0

inlink_dscr_bf1: INLINK_DSCR_BF1

0x50 - I2S_INLINK_DSCR_BF1

outlink_dscr: OUTLINK_DSCR

0x54 - I2S_OUTLINK_DSCR

outlink_dscr_bf0: OUTLINK_DSCR_BF0

0x58 - I2S_OUTLINK_DSCR_BF0

outlink_dscr_bf1: OUTLINK_DSCR_BF1

0x5c - I2S_OUTLINK_DSCR_BF1

lc_conf: LC_CONF

0x60 - I2S_LC_CONF

outfifo_push: OUTFIFO_PUSH

0x64 - I2S_OUTFIFO_PUSH

infifo_pop: INFIFO_POP

0x68 - I2S_INFIFO_POP

lc_state0: LC_STATE0

0x6c - I2S_LC_STATE0

lc_state1: LC_STATE1

0x70 - I2S_LC_STATE1

lc_hung_conf: LC_HUNG_CONF

0x74 - I2S_LC_HUNG_CONF

cvsd_conf0: CVSD_CONF0

0x80 - I2S_CVSD_CONF0

cvsd_conf1: CVSD_CONF1

0x84 - I2S_CVSD_CONF1

cvsd_conf2: CVSD_CONF2

0x88 - I2S_CVSD_CONF2

plc_conf0: PLC_CONF0

0x8c - I2S_PLC_CONF0

plc_conf1: PLC_CONF1

0x90 - I2S_PLC_CONF1

plc_conf2: PLC_CONF2

0x94 - I2S_PLC_CONF2

esco_conf0: ESCO_CONF0

0x98 - I2S_ESCO_CONF0

sco_conf0: SCO_CONF0

0x9c - I2S_SCO_CONF0

conf1: CONF1

0xa0 - I2S_CONF1

pd_conf: PD_CONF

0xa4 - I2S_PD_CONF

conf2: CONF2

0xa8 - I2S_CONF2

clkm_conf: CLKM_CONF

0xac - I2S_CLKM_CONF

sample_rate_conf: SAMPLE_RATE_CONF

0xb0 - I2S_SAMPLE_RATE_CONF

pdm_conf: PDM_CONF

0xb4 - I2S_PDM_CONF

pdm_freq_conf: PDM_FREQ_CONF

0xb8 - I2S_PDM_FREQ_CONF

state: STATE

0xbc - I2S_STATE

date: DATE

0xfc - I2S_DATE

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