Struct esp32::pwm0::RegisterBlock

source · 
#[repr(C)]
pub struct RegisterBlock {
Show 74 fields
    pub clk_cfg: CLK_CFG,
    pub timer0_cfg0: TIMER0_CFG0,
    pub timer0_cfg1: TIMER0_CFG1,
    pub timer0_sync: TIMER0_SYNC,
    pub timer0_status: TIMER0_STATUS,
    pub timer1_cfg0: TIMER1_CFG0,
    pub timer1_cfg1: TIMER1_CFG1,
    pub timer1_sync: TIMER1_SYNC,
    pub timer1_status: TIMER1_STATUS,
    pub timer2_cfg0: TIMER2_CFG0,
    pub timer2_cfg1: TIMER2_CFG1,
    pub timer2_sync: TIMER2_SYNC,
    pub timer2_status: TIMER2_STATUS,
    pub timer_synci_cfg: TIMER_SYNCI_CFG,
    pub operator_timersel: OPERATOR_TIMERSEL,
    pub gen0_stmp_cfg: GEN0_STMP_CFG,
    pub gen0_tstmp_a: GEN0_TSTMP_A,
    pub gen0_tstmp_b: GEN0_TSTMP_B,
    pub gen0_cfg0: GEN0_CFG0,
    pub gen0_force: GEN0_FORCE,
    pub gen0_a: GEN0_A,
    pub gen0_b: GEN0_B,
    pub dt0_cfg: DT0_CFG,
    pub dt0_fed_cfg: DT0_FED_CFG,
    pub dt0_red_cfg: DT0_RED_CFG,
    pub carrier0_cfg: CARRIER0_CFG,
    pub fh0_cfg0: FH0_CFG0,
    pub fh0_cfg1: FH0_CFG1,
    pub fh0_status: FH0_STATUS,
    pub gen1_stmp_cfg: GEN1_STMP_CFG,
    pub gen1_tstmp_a: GEN1_TSTMP_A,
    pub gen1_tstmp_b: GEN1_TSTMP_B,
    pub gen1_cfg0: GEN1_CFG0,
    pub gen1_force: GEN1_FORCE,
    pub gen1_a: GEN1_A,
    pub gen1_b: GEN1_B,
    pub dt1_cfg: DT1_CFG,
    pub dt1_fed_cfg: DT1_FED_CFG,
    pub dt1_red_cfg: DT1_RED_CFG,
    pub carrier1_cfg: CARRIER1_CFG,
    pub fh1_cfg0: FH1_CFG0,
    pub fh1_cfg1: FH1_CFG1,
    pub fh1_status: FH1_STATUS,
    pub gen2_stmp_cfg: GEN2_STMP_CFG,
    pub gen2_tstmp_a: GEN2_TSTMP_A,
    pub gen2_tstmp_b: GEN2_TSTMP_B,
    pub gen2_cfg0: GEN2_CFG0,
    pub gen2_force: GEN2_FORCE,
    pub gen2_a: GEN2_A,
    pub gen2_b: GEN2_B,
    pub dt2_cfg: DT2_CFG,
    pub dt2_fed_cfg: DT2_FED_CFG,
    pub dt2_red_cfg: DT2_RED_CFG,
    pub carrier2_cfg: CARRIER2_CFG,
    pub fh2_cfg0: FH2_CFG0,
    pub fh2_cfg1: FH2_CFG1,
    pub fh2_status: FH2_STATUS,
    pub fault_detect: FAULT_DETECT,
    pub cap_timer_cfg: CAP_TIMER_CFG,
    pub cap_timer_phase: CAP_TIMER_PHASE,
    pub cap_ch0_cfg: CAP_CH0_CFG,
    pub cap_ch1_cfg: CAP_CH1_CFG,
    pub cap_ch2_cfg: CAP_CH2_CFG,
    pub cap_ch0: CAP_CH0,
    pub cap_ch1: CAP_CH1,
    pub cap_ch2: CAP_CH2,
    pub cap_status: CAP_STATUS,
    pub update_cfg: UPDATE_CFG,
    pub int_ena: INT_ENA,
    pub int_raw: INT_RAW,
    pub int_st: INT_ST,
    pub int_clr: INT_CLR,
    pub clk: CLK,
    pub version: VERSION,

}
Expand description

Register block

Fields§

§clk_cfg: CLK_CFG

0x00 -

§timer0_cfg0: TIMER0_CFG0

0x04 -

§timer0_cfg1: TIMER0_CFG1

0x08 -

§timer0_sync: TIMER0_SYNC

0x0c -

§timer0_status: TIMER0_STATUS

0x10 -

§timer1_cfg0: TIMER1_CFG0

0x14 -

§timer1_cfg1: TIMER1_CFG1

0x18 -

§timer1_sync: TIMER1_SYNC

0x1c -

§timer1_status: TIMER1_STATUS

0x20 -

§timer2_cfg0: TIMER2_CFG0

0x24 -

§timer2_cfg1: TIMER2_CFG1

0x28 -

§timer2_sync: TIMER2_SYNC

0x2c -

§timer2_status: TIMER2_STATUS

0x30 -

§timer_synci_cfg: TIMER_SYNCI_CFG

0x34 -

§operator_timersel: OPERATOR_TIMERSEL

0x38 -

§gen0_stmp_cfg: GEN0_STMP_CFG

0x3c -

§gen0_tstmp_a: GEN0_TSTMP_A

0x40 -

§gen0_tstmp_b: GEN0_TSTMP_B

0x44 -

§gen0_cfg0: GEN0_CFG0

0x48 -

§gen0_force: GEN0_FORCE

0x4c -

§gen0_a: GEN0_A

0x50 -

§gen0_b: GEN0_B

0x54 -

§dt0_cfg: DT0_CFG

0x58 -

§dt0_fed_cfg: DT0_FED_CFG

0x5c -

§dt0_red_cfg: DT0_RED_CFG

0x60 -

§carrier0_cfg: CARRIER0_CFG

0x64 -

§fh0_cfg0: FH0_CFG0

0x68 -

§fh0_cfg1: FH0_CFG1

0x6c -

§fh0_status: FH0_STATUS

0x70 -

§gen1_stmp_cfg: GEN1_STMP_CFG

0x74 -

§gen1_tstmp_a: GEN1_TSTMP_A

0x78 -

§gen1_tstmp_b: GEN1_TSTMP_B

0x7c -

§gen1_cfg0: GEN1_CFG0

0x80 -

§gen1_force: GEN1_FORCE

0x84 -

§gen1_a: GEN1_A

0x88 -

§gen1_b: GEN1_B

0x8c -

§dt1_cfg: DT1_CFG

0x90 -

§dt1_fed_cfg: DT1_FED_CFG

0x94 -

§dt1_red_cfg: DT1_RED_CFG

0x98 -

§carrier1_cfg: CARRIER1_CFG

0x9c -

§fh1_cfg0: FH1_CFG0

0xa0 -

§fh1_cfg1: FH1_CFG1

0xa4 -

§fh1_status: FH1_STATUS

0xa8 -

§gen2_stmp_cfg: GEN2_STMP_CFG

0xac -

§gen2_tstmp_a: GEN2_TSTMP_A

0xb0 -

§gen2_tstmp_b: GEN2_TSTMP_B

0xb4 -

§gen2_cfg0: GEN2_CFG0

0xb8 -

§gen2_force: GEN2_FORCE

0xbc -

§gen2_a: GEN2_A

0xc0 -

§gen2_b: GEN2_B

0xc4 -

§dt2_cfg: DT2_CFG

0xc8 -

§dt2_fed_cfg: DT2_FED_CFG

0xcc -

§dt2_red_cfg: DT2_RED_CFG

0xd0 -

§carrier2_cfg: CARRIER2_CFG

0xd4 -

§fh2_cfg0: FH2_CFG0

0xd8 -

§fh2_cfg1: FH2_CFG1

0xdc -

§fh2_status: FH2_STATUS

0xe0 -

§fault_detect: FAULT_DETECT

0xe4 -

§cap_timer_cfg: CAP_TIMER_CFG

0xe8 -

§cap_timer_phase: CAP_TIMER_PHASE

0xec -

§cap_ch0_cfg: CAP_CH0_CFG

0xf0 -

§cap_ch1_cfg: CAP_CH1_CFG

0xf4 -

§cap_ch2_cfg: CAP_CH2_CFG

0xf8 -

§cap_ch0: CAP_CH0

0xfc -

§cap_ch1: CAP_CH1

0x100 -

§cap_ch2: CAP_CH2

0x104 -

§cap_status: CAP_STATUS

0x108 -

§update_cfg: UPDATE_CFG

0x10c -

§int_ena: INT_ENA

0x110 -

§int_raw: INT_RAW

0x114 -

§int_st: INT_ST

0x118 -

§int_clr: INT_CLR

0x11c -

§clk: CLK

0x120 -

§version: VERSION

0x124 -

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