Expand description
Structs
Field CK_OUT_HIGH_MODE reader - modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits.
Field CK_OUT_HIGH_MODE writer - modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits.
Field CK_OUT_LOW_MODE reader - modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits.
Field CK_OUT_LOW_MODE writer - modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits.
Field CS_DELAY_MODE reader - spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle
Field CS_DELAY_MODE writer - spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle
Field CS_DELAY_NUM reader - spi_cs signal is delayed by system clock cycles
Field CS_DELAY_NUM writer - spi_cs signal is delayed by system clock cycles
This register you can [read]
(crate::generic::Reg::read), [write_with_zero]
(crate::generic::Reg::write_with_zero), [reset]
(crate::generic::Reg::reset), write
(crate::generic::Reg::write), [modify]
(crate::generic::Reg::modify). See [API]
(https://docs.rs/svd2rust/#read–modify–write-api).
Field HOLD_TIME reader - delay cycles of cs pin by spi clock, this bits combined with spi_cs_hold bit.
Field HOLD_TIME writer - delay cycles of cs pin by spi clock, this bits combined with spi_cs_hold bit.
Field MISO_DELAY_MODE reader - MISO signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle
Field MISO_DELAY_MODE writer - MISO signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle
Field MISO_DELAY_NUM reader - MISO signals are delayed by system clock cycles
Field MISO_DELAY_NUM writer - MISO signals are delayed by system clock cycles
Field MOSI_DELAY_MODE reader - MOSI signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle
Field MOSI_DELAY_MODE writer - MOSI signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle
Field MOSI_DELAY_NUM reader - MOSI signals are delayed by system clock cycles
Field MOSI_DELAY_NUM writer - MOSI signals are delayed by system clock cycles
Register CTRL2 reader
Field SETUP_TIME reader - (cycles-1) of ¡°prepare¡± phase by spi clock, this bits combined with spi_cs_setup bit.
Field SETUP_TIME writer - (cycles-1) of ¡°prepare¡± phase by spi clock, this bits combined with spi_cs_setup bit.
Register CTRL2 writer