[][src]Struct esp32::slc::RegisterBlock

#[repr(C)]pub struct RegisterBlock {
    pub conf0: Reg<CONF0_SPEC>,
    pub _0int_raw: Reg<_0INT_RAW_SPEC>,
    pub _0int_st: Reg<_0INT_ST_SPEC>,
    pub _0int_ena: Reg<_0INT_ENA_SPEC>,
    pub _0int_clr: Reg<_0INT_CLR_SPEC>,
    pub _1int_raw: Reg<_1INT_RAW_SPEC>,
    pub _1int_st: Reg<_1INT_ST_SPEC>,
    pub _1int_ena: Reg<_1INT_ENA_SPEC>,
    pub _1int_clr: Reg<_1INT_CLR_SPEC>,
    pub rx_status: Reg<RX_STATUS_SPEC>,
    pub _0rxfifo_push: Reg<_0RXFIFO_PUSH_SPEC>,
    pub _1rxfifo_push: Reg<_1RXFIFO_PUSH_SPEC>,
    pub tx_status: Reg<TX_STATUS_SPEC>,
    pub _0txfifo_pop: Reg<_0TXFIFO_POP_SPEC>,
    pub _1txfifo_pop: Reg<_1TXFIFO_POP_SPEC>,
    pub _0rx_link: Reg<_0RX_LINK_SPEC>,
    pub _0tx_link: Reg<_0TX_LINK_SPEC>,
    pub _1rx_link: Reg<_1RX_LINK_SPEC>,
    pub _1tx_link: Reg<_1TX_LINK_SPEC>,
    pub intvec_tohost: Reg<INTVEC_TOHOST_SPEC>,
    pub _0token0: Reg<_0TOKEN0_SPEC>,
    pub _0token1: Reg<_0TOKEN1_SPEC>,
    pub _1token0: Reg<_1TOKEN0_SPEC>,
    pub _1token1: Reg<_1TOKEN1_SPEC>,
    pub conf1: Reg<CONF1_SPEC>,
    pub _0_state0: Reg<_0_STATE0_SPEC>,
    pub _0_state1: Reg<_0_STATE1_SPEC>,
    pub _1_state0: Reg<_1_STATE0_SPEC>,
    pub _1_state1: Reg<_1_STATE1_SPEC>,
    pub bridge_conf: Reg<BRIDGE_CONF_SPEC>,
    pub _0_to_eof_des_addr: Reg<_0_TO_EOF_DES_ADDR_SPEC>,
    pub _0_tx_eof_des_addr: Reg<_0_TX_EOF_DES_ADDR_SPEC>,
    pub _0_to_eof_bfr_des_addr: Reg<_0_TO_EOF_BFR_DES_ADDR_SPEC>,
    pub _1_to_eof_des_addr: Reg<_1_TO_EOF_DES_ADDR_SPEC>,
    pub _1_tx_eof_des_addr: Reg<_1_TX_EOF_DES_ADDR_SPEC>,
    pub _1_to_eof_bfr_des_addr: Reg<_1_TO_EOF_BFR_DES_ADDR_SPEC>,
    pub ahb_test: Reg<AHB_TEST_SPEC>,
    pub sdio_st: Reg<SDIO_ST_SPEC>,
    pub rx_dscr_conf: Reg<RX_DSCR_CONF_SPEC>,
    pub _0_txlink_dscr: Reg<_0_TXLINK_DSCR_SPEC>,
    pub _0_txlink_dscr_bf0: Reg<_0_TXLINK_DSCR_BF0_SPEC>,
    pub _0_txlink_dscr_bf1: Reg<_0_TXLINK_DSCR_BF1_SPEC>,
    pub _0_rxlink_dscr: Reg<_0_RXLINK_DSCR_SPEC>,
    pub _0_rxlink_dscr_bf0: Reg<_0_RXLINK_DSCR_BF0_SPEC>,
    pub _0_rxlink_dscr_bf1: Reg<_0_RXLINK_DSCR_BF1_SPEC>,
    pub _1_txlink_dscr: Reg<_1_TXLINK_DSCR_SPEC>,
    pub _1_txlink_dscr_bf0: Reg<_1_TXLINK_DSCR_BF0_SPEC>,
    pub _1_txlink_dscr_bf1: Reg<_1_TXLINK_DSCR_BF1_SPEC>,
    pub _1_rxlink_dscr: Reg<_1_RXLINK_DSCR_SPEC>,
    pub _1_rxlink_dscr_bf0: Reg<_1_RXLINK_DSCR_BF0_SPEC>,
    pub _1_rxlink_dscr_bf1: Reg<_1_RXLINK_DSCR_BF1_SPEC>,
    pub _0_tx_erreof_des_addr: Reg<_0_TX_ERREOF_DES_ADDR_SPEC>,
    pub _1_tx_erreof_des_addr: Reg<_1_TX_ERREOF_DES_ADDR_SPEC>,
    pub token_lat: Reg<TOKEN_LAT_SPEC>,
    pub tx_dscr_conf: Reg<TX_DSCR_CONF_SPEC>,
    pub cmd_infor0: Reg<CMD_INFOR0_SPEC>,
    pub cmd_infor1: Reg<CMD_INFOR1_SPEC>,
    pub _0_len_conf: Reg<_0_LEN_CONF_SPEC>,
    pub _0_length: Reg<_0_LENGTH_SPEC>,
    pub _0_txpkt_h_dscr: Reg<_0_TXPKT_H_DSCR_SPEC>,
    pub _0_txpkt_e_dscr: Reg<_0_TXPKT_E_DSCR_SPEC>,
    pub _0_rxpkt_h_dscr: Reg<_0_RXPKT_H_DSCR_SPEC>,
    pub _0_rxpkt_e_dscr: Reg<_0_RXPKT_E_DSCR_SPEC>,
    pub _0_txpktu_h_dscr: Reg<_0_TXPKTU_H_DSCR_SPEC>,
    pub _0_txpktu_e_dscr: Reg<_0_TXPKTU_E_DSCR_SPEC>,
    pub _0_rxpktu_h_dscr: Reg<_0_RXPKTU_H_DSCR_SPEC>,
    pub _0_rxpktu_e_dscr: Reg<_0_RXPKTU_E_DSCR_SPEC>,
    pub seq_position: Reg<SEQ_POSITION_SPEC>,
    pub _0_dscr_rec_conf: Reg<_0_DSCR_REC_CONF_SPEC>,
    pub sdio_crc_st0: Reg<SDIO_CRC_ST0_SPEC>,
    pub sdio_crc_st1: Reg<SDIO_CRC_ST1_SPEC>,
    pub _0_eof_start_des: Reg<_0_EOF_START_DES_SPEC>,
    pub _0_push_dscr_addr: Reg<_0_PUSH_DSCR_ADDR_SPEC>,
    pub _0_done_dscr_addr: Reg<_0_DONE_DSCR_ADDR_SPEC>,
    pub _0_sub_start_des: Reg<_0_SUB_START_DES_SPEC>,
    pub _0_dscr_cnt: Reg<_0_DSCR_CNT_SPEC>,
    pub _0_len_lim_conf: Reg<_0_LEN_LIM_CONF_SPEC>,
    pub _0int_st1: Reg<_0INT_ST1_SPEC>,
    pub _0int_ena1: Reg<_0INT_ENA1_SPEC>,
    pub _1int_st1: Reg<_1INT_ST1_SPEC>,
    pub _1int_ena1: Reg<_1INT_ENA1_SPEC>,
    pub date: Reg<DATE_SPEC>,
    pub id: Reg<ID_SPEC>,
    // some fields omitted
}

Register block

Fields

conf0: Reg<CONF0_SPEC>

0x00 - SLC_CONF0

_0int_raw: Reg<_0INT_RAW_SPEC>

0x04 - SLC_0INT_RAW

_0int_st: Reg<_0INT_ST_SPEC>

0x08 - SLC_0INT_ST

_0int_ena: Reg<_0INT_ENA_SPEC>

0x0c - SLC_0INT_ENA

_0int_clr: Reg<_0INT_CLR_SPEC>

0x10 - SLC_0INT_CLR

_1int_raw: Reg<_1INT_RAW_SPEC>

0x14 - SLC_1INT_RAW

_1int_st: Reg<_1INT_ST_SPEC>

0x18 - SLC_1INT_ST

_1int_ena: Reg<_1INT_ENA_SPEC>

0x1c - SLC_1INT_ENA

_1int_clr: Reg<_1INT_CLR_SPEC>

0x20 - SLC_1INT_CLR

rx_status: Reg<RX_STATUS_SPEC>

0x24 - SLC_RX_STATUS

_0rxfifo_push: Reg<_0RXFIFO_PUSH_SPEC>

0x28 - SLC_0RXFIFO_PUSH

_1rxfifo_push: Reg<_1RXFIFO_PUSH_SPEC>

0x2c - SLC_1RXFIFO_PUSH

tx_status: Reg<TX_STATUS_SPEC>

0x30 - SLC_TX_STATUS

_0txfifo_pop: Reg<_0TXFIFO_POP_SPEC>

0x34 - SLC_0TXFIFO_POP

_1txfifo_pop: Reg<_1TXFIFO_POP_SPEC>

0x38 - SLC_1TXFIFO_POP

_0rx_link: Reg<_0RX_LINK_SPEC>

0x3c - SLC_0RX_LINK

_0tx_link: Reg<_0TX_LINK_SPEC>

0x40 - SLC_0TX_LINK

_1rx_link: Reg<_1RX_LINK_SPEC>

0x44 - SLC_1RX_LINK

_1tx_link: Reg<_1TX_LINK_SPEC>

0x48 - SLC_1TX_LINK

intvec_tohost: Reg<INTVEC_TOHOST_SPEC>

0x4c - SLC_INTVEC_TOHOST

_0token0: Reg<_0TOKEN0_SPEC>

0x50 - SLC_0TOKEN0

_0token1: Reg<_0TOKEN1_SPEC>

0x54 - SLC_0TOKEN1

_1token0: Reg<_1TOKEN0_SPEC>

0x58 - SLC_1TOKEN0

_1token1: Reg<_1TOKEN1_SPEC>

0x5c - SLC_1TOKEN1

conf1: Reg<CONF1_SPEC>

0x60 - SLC_CONF1

_0_state0: Reg<_0_STATE0_SPEC>

0x64 - SLC_0_STATE0

_0_state1: Reg<_0_STATE1_SPEC>

0x68 - SLC_0_STATE1

_1_state0: Reg<_1_STATE0_SPEC>

0x6c - SLC_1_STATE0

_1_state1: Reg<_1_STATE1_SPEC>

0x70 - SLC_1_STATE1

bridge_conf: Reg<BRIDGE_CONF_SPEC>

0x74 - SLC_BRIDGE_CONF

_0_to_eof_des_addr: Reg<_0_TO_EOF_DES_ADDR_SPEC>

0x78 - SLC_0_TO_EOF_DES_ADDR

_0_tx_eof_des_addr: Reg<_0_TX_EOF_DES_ADDR_SPEC>

0x7c - SLC_0_TX_EOF_DES_ADDR

_0_to_eof_bfr_des_addr: Reg<_0_TO_EOF_BFR_DES_ADDR_SPEC>

0x80 - SLC_0_TO_EOF_BFR_DES_ADDR

_1_to_eof_des_addr: Reg<_1_TO_EOF_DES_ADDR_SPEC>

0x84 - SLC_1_TO_EOF_DES_ADDR

_1_tx_eof_des_addr: Reg<_1_TX_EOF_DES_ADDR_SPEC>

0x88 - SLC_1_TX_EOF_DES_ADDR

_1_to_eof_bfr_des_addr: Reg<_1_TO_EOF_BFR_DES_ADDR_SPEC>

0x8c - SLC_1_TO_EOF_BFR_DES_ADDR

ahb_test: Reg<AHB_TEST_SPEC>

0x90 - SLC_AHB_TEST

sdio_st: Reg<SDIO_ST_SPEC>

0x94 - SLC_SDIO_ST

rx_dscr_conf: Reg<RX_DSCR_CONF_SPEC>

0x98 - SLC_RX_DSCR_CONF

_0_txlink_dscr: Reg<_0_TXLINK_DSCR_SPEC>

0x9c - SLC_0_TXLINK_DSCR

_0_txlink_dscr_bf0: Reg<_0_TXLINK_DSCR_BF0_SPEC>

0xa0 - SLC_0_TXLINK_DSCR_BF0

_0_txlink_dscr_bf1: Reg<_0_TXLINK_DSCR_BF1_SPEC>

0xa4 - SLC_0_TXLINK_DSCR_BF1

_0_rxlink_dscr: Reg<_0_RXLINK_DSCR_SPEC>

0xa8 - SLC_0_RXLINK_DSCR

_0_rxlink_dscr_bf0: Reg<_0_RXLINK_DSCR_BF0_SPEC>

0xac - SLC_0_RXLINK_DSCR_BF0

_0_rxlink_dscr_bf1: Reg<_0_RXLINK_DSCR_BF1_SPEC>

0xb0 - SLC_0_RXLINK_DSCR_BF1

_1_txlink_dscr: Reg<_1_TXLINK_DSCR_SPEC>

0xb4 - SLC_1_TXLINK_DSCR

_1_txlink_dscr_bf0: Reg<_1_TXLINK_DSCR_BF0_SPEC>

0xb8 - SLC_1_TXLINK_DSCR_BF0

_1_txlink_dscr_bf1: Reg<_1_TXLINK_DSCR_BF1_SPEC>

0xbc - SLC_1_TXLINK_DSCR_BF1

_1_rxlink_dscr: Reg<_1_RXLINK_DSCR_SPEC>

0xc0 - SLC_1_RXLINK_DSCR

_1_rxlink_dscr_bf0: Reg<_1_RXLINK_DSCR_BF0_SPEC>

0xc4 - SLC_1_RXLINK_DSCR_BF0

_1_rxlink_dscr_bf1: Reg<_1_RXLINK_DSCR_BF1_SPEC>

0xc8 - SLC_1_RXLINK_DSCR_BF1

_0_tx_erreof_des_addr: Reg<_0_TX_ERREOF_DES_ADDR_SPEC>

0xcc - SLC_0_TX_ERREOF_DES_ADDR

_1_tx_erreof_des_addr: Reg<_1_TX_ERREOF_DES_ADDR_SPEC>

0xd0 - SLC_1_TX_ERREOF_DES_ADDR

token_lat: Reg<TOKEN_LAT_SPEC>

0xd4 - SLC_TOKEN_LAT

tx_dscr_conf: Reg<TX_DSCR_CONF_SPEC>

0xd8 - SLC_TX_DSCR_CONF

cmd_infor0: Reg<CMD_INFOR0_SPEC>

0xdc - SLC_CMD_INFOR0

cmd_infor1: Reg<CMD_INFOR1_SPEC>

0xe0 - SLC_CMD_INFOR1

_0_len_conf: Reg<_0_LEN_CONF_SPEC>

0xe4 - SLC_0_LEN_CONF

_0_length: Reg<_0_LENGTH_SPEC>

0xe8 - SLC_0_LENGTH

_0_txpkt_h_dscr: Reg<_0_TXPKT_H_DSCR_SPEC>

0xec - SLC_0_TXPKT_H_DSCR

_0_txpkt_e_dscr: Reg<_0_TXPKT_E_DSCR_SPEC>

0xf0 - SLC_0_TXPKT_E_DSCR

_0_rxpkt_h_dscr: Reg<_0_RXPKT_H_DSCR_SPEC>

0xf4 - SLC_0_RXPKT_H_DSCR

_0_rxpkt_e_dscr: Reg<_0_RXPKT_E_DSCR_SPEC>

0xf8 - SLC_0_RXPKT_E_DSCR

_0_txpktu_h_dscr: Reg<_0_TXPKTU_H_DSCR_SPEC>

0xfc - SLC_0_TXPKTU_H_DSCR

_0_txpktu_e_dscr: Reg<_0_TXPKTU_E_DSCR_SPEC>

0x100 - SLC_0_TXPKTU_E_DSCR

_0_rxpktu_h_dscr: Reg<_0_RXPKTU_H_DSCR_SPEC>

0x104 - SLC_0_RXPKTU_H_DSCR

_0_rxpktu_e_dscr: Reg<_0_RXPKTU_E_DSCR_SPEC>

0x108 - SLC_0_RXPKTU_E_DSCR

seq_position: Reg<SEQ_POSITION_SPEC>

0x114 - SLC_SEQ_POSITION

_0_dscr_rec_conf: Reg<_0_DSCR_REC_CONF_SPEC>

0x118 - SLC_0_DSCR_REC_CONF

sdio_crc_st0: Reg<SDIO_CRC_ST0_SPEC>

0x11c - SLC_SDIO_CRC_ST0

sdio_crc_st1: Reg<SDIO_CRC_ST1_SPEC>

0x120 - SLC_SDIO_CRC_ST1

_0_eof_start_des: Reg<_0_EOF_START_DES_SPEC>

0x124 - SLC_0_EOF_START_DES

_0_push_dscr_addr: Reg<_0_PUSH_DSCR_ADDR_SPEC>

0x128 - SLC_0_PUSH_DSCR_ADDR

_0_done_dscr_addr: Reg<_0_DONE_DSCR_ADDR_SPEC>

0x12c - SLC_0_DONE_DSCR_ADDR

_0_sub_start_des: Reg<_0_SUB_START_DES_SPEC>

0x130 - SLC_0_SUB_START_DES

_0_dscr_cnt: Reg<_0_DSCR_CNT_SPEC>

0x134 - SLC_0_DSCR_CNT

_0_len_lim_conf: Reg<_0_LEN_LIM_CONF_SPEC>

0x138 - SLC_0_LEN_LIM_CONF

_0int_st1: Reg<_0INT_ST1_SPEC>

0x13c - SLC_0INT_ST1

_0int_ena1: Reg<_0INT_ENA1_SPEC>

0x140 - SLC_0INT_ENA1

_1int_st1: Reg<_1INT_ST1_SPEC>

0x144 - SLC_1INT_ST1

_1int_ena1: Reg<_1INT_ENA1_SPEC>

0x148 - SLC_1INT_ENA1

date: Reg<DATE_SPEC>

0x1f8 - SLC_DATE

id: Reg<ID_SPEC>

0x1fc - SLC_ID

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impl<T> Any for T where
    T: 'static + ?Sized
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impl<T> Borrow<T> for T where
    T: ?Sized
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impl<T> BorrowMut<T> for T where
    T: ?Sized
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impl<T> From<T> for T[src]

impl<T, U> Into<U> for T where
    U: From<T>, 
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impl<T, U> TryFrom<U> for T where
    U: Into<T>, 
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type Error = Infallible

The type returned in the event of a conversion error.

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, 
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type Error = <U as TryFrom<T>>::Error

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