[][src]Struct esp32::i2s::RegisterBlock

#[repr(C)]pub struct RegisterBlock {
    pub conf: Reg<CONF_SPEC>,
    pub int_raw: Reg<INT_RAW_SPEC>,
    pub int_st: Reg<INT_ST_SPEC>,
    pub int_ena: Reg<INT_ENA_SPEC>,
    pub int_clr: Reg<INT_CLR_SPEC>,
    pub timing: Reg<TIMING_SPEC>,
    pub fifo_conf: Reg<FIFO_CONF_SPEC>,
    pub rxeof_num: Reg<RXEOF_NUM_SPEC>,
    pub conf_sigle_data: Reg<CONF_SIGLE_DATA_SPEC>,
    pub conf_chan: Reg<CONF_CHAN_SPEC>,
    pub out_link: Reg<OUT_LINK_SPEC>,
    pub in_link: Reg<IN_LINK_SPEC>,
    pub out_eof_des_addr: Reg<OUT_EOF_DES_ADDR_SPEC>,
    pub in_eof_des_addr: Reg<IN_EOF_DES_ADDR_SPEC>,
    pub out_eof_bfr_des_addr: Reg<OUT_EOF_BFR_DES_ADDR_SPEC>,
    pub ahb_test: Reg<AHB_TEST_SPEC>,
    pub inlink_dscr: Reg<INLINK_DSCR_SPEC>,
    pub inlink_dscr_bf0: Reg<INLINK_DSCR_BF0_SPEC>,
    pub inlink_dscr_bf1: Reg<INLINK_DSCR_BF1_SPEC>,
    pub outlink_dscr: Reg<OUTLINK_DSCR_SPEC>,
    pub outlink_dscr_bf0: Reg<OUTLINK_DSCR_BF0_SPEC>,
    pub outlink_dscr_bf1: Reg<OUTLINK_DSCR_BF1_SPEC>,
    pub lc_conf: Reg<LC_CONF_SPEC>,
    pub outfifo_push: Reg<OUTFIFO_PUSH_SPEC>,
    pub infifo_pop: Reg<INFIFO_POP_SPEC>,
    pub lc_state0: Reg<LC_STATE0_SPEC>,
    pub lc_state1: Reg<LC_STATE1_SPEC>,
    pub lc_hung_conf: Reg<LC_HUNG_CONF_SPEC>,
    pub cvsd_conf0: Reg<CVSD_CONF0_SPEC>,
    pub cvsd_conf1: Reg<CVSD_CONF1_SPEC>,
    pub cvsd_conf2: Reg<CVSD_CONF2_SPEC>,
    pub plc_conf0: Reg<PLC_CONF0_SPEC>,
    pub plc_conf1: Reg<PLC_CONF1_SPEC>,
    pub plc_conf2: Reg<PLC_CONF2_SPEC>,
    pub esco_conf0: Reg<ESCO_CONF0_SPEC>,
    pub sco_conf0: Reg<SCO_CONF0_SPEC>,
    pub conf1: Reg<CONF1_SPEC>,
    pub pd_conf: Reg<PD_CONF_SPEC>,
    pub conf2: Reg<CONF2_SPEC>,
    pub clkm_conf: Reg<CLKM_CONF_SPEC>,
    pub sample_rate_conf: Reg<SAMPLE_RATE_CONF_SPEC>,
    pub pdm_conf: Reg<PDM_CONF_SPEC>,
    pub pdm_freq_conf: Reg<PDM_FREQ_CONF_SPEC>,
    pub state: Reg<STATE_SPEC>,
    pub date: Reg<DATE_SPEC>,
    // some fields omitted
}

Register block

Fields

conf: Reg<CONF_SPEC>

0x08 - I2S_CONF

int_raw: Reg<INT_RAW_SPEC>

0x0c - I2S_INT_RAW

int_st: Reg<INT_ST_SPEC>

0x10 - I2S_INT_ST

int_ena: Reg<INT_ENA_SPEC>

0x14 - I2S_INT_ENA

int_clr: Reg<INT_CLR_SPEC>

0x18 - I2S_INT_CLR

timing: Reg<TIMING_SPEC>

0x1c - I2S_TIMING

fifo_conf: Reg<FIFO_CONF_SPEC>

0x20 - I2S_FIFO_CONF

rxeof_num: Reg<RXEOF_NUM_SPEC>

0x24 - I2S_RXEOF_NUM

conf_sigle_data: Reg<CONF_SIGLE_DATA_SPEC>

0x28 - I2S_CONF_SIGLE_DATA

conf_chan: Reg<CONF_CHAN_SPEC>

0x2c - I2S_CONF_CHAN

out_link: Reg<OUT_LINK_SPEC>

0x30 - I2S_OUT_LINK

in_link: Reg<IN_LINK_SPEC>

0x34 - I2S_IN_LINK

out_eof_des_addr: Reg<OUT_EOF_DES_ADDR_SPEC>

0x38 - I2S_OUT_EOF_DES_ADDR

in_eof_des_addr: Reg<IN_EOF_DES_ADDR_SPEC>

0x3c - I2S_IN_EOF_DES_ADDR

out_eof_bfr_des_addr: Reg<OUT_EOF_BFR_DES_ADDR_SPEC>

0x40 - I2S_OUT_EOF_BFR_DES_ADDR

ahb_test: Reg<AHB_TEST_SPEC>

0x44 - I2S_AHB_TEST

inlink_dscr: Reg<INLINK_DSCR_SPEC>

0x48 - I2S_INLINK_DSCR

inlink_dscr_bf0: Reg<INLINK_DSCR_BF0_SPEC>

0x4c - I2S_INLINK_DSCR_BF0

inlink_dscr_bf1: Reg<INLINK_DSCR_BF1_SPEC>

0x50 - I2S_INLINK_DSCR_BF1

outlink_dscr: Reg<OUTLINK_DSCR_SPEC>

0x54 - I2S_OUTLINK_DSCR

outlink_dscr_bf0: Reg<OUTLINK_DSCR_BF0_SPEC>

0x58 - I2S_OUTLINK_DSCR_BF0

outlink_dscr_bf1: Reg<OUTLINK_DSCR_BF1_SPEC>

0x5c - I2S_OUTLINK_DSCR_BF1

lc_conf: Reg<LC_CONF_SPEC>

0x60 - I2S_LC_CONF

outfifo_push: Reg<OUTFIFO_PUSH_SPEC>

0x64 - I2S_OUTFIFO_PUSH

infifo_pop: Reg<INFIFO_POP_SPEC>

0x68 - I2S_INFIFO_POP

lc_state0: Reg<LC_STATE0_SPEC>

0x6c - I2S_LC_STATE0

lc_state1: Reg<LC_STATE1_SPEC>

0x70 - I2S_LC_STATE1

lc_hung_conf: Reg<LC_HUNG_CONF_SPEC>

0x74 - I2S_LC_HUNG_CONF

cvsd_conf0: Reg<CVSD_CONF0_SPEC>

0x80 - I2S_CVSD_CONF0

cvsd_conf1: Reg<CVSD_CONF1_SPEC>

0x84 - I2S_CVSD_CONF1

cvsd_conf2: Reg<CVSD_CONF2_SPEC>

0x88 - I2S_CVSD_CONF2

plc_conf0: Reg<PLC_CONF0_SPEC>

0x8c - I2S_PLC_CONF0

plc_conf1: Reg<PLC_CONF1_SPEC>

0x90 - I2S_PLC_CONF1

plc_conf2: Reg<PLC_CONF2_SPEC>

0x94 - I2S_PLC_CONF2

esco_conf0: Reg<ESCO_CONF0_SPEC>

0x98 - I2S_ESCO_CONF0

sco_conf0: Reg<SCO_CONF0_SPEC>

0x9c - I2S_SCO_CONF0

conf1: Reg<CONF1_SPEC>

0xa0 - I2S_CONF1

pd_conf: Reg<PD_CONF_SPEC>

0xa4 - I2S_PD_CONF

conf2: Reg<CONF2_SPEC>

0xa8 - I2S_CONF2

clkm_conf: Reg<CLKM_CONF_SPEC>

0xac - I2S_CLKM_CONF

sample_rate_conf: Reg<SAMPLE_RATE_CONF_SPEC>

0xb0 - I2S_SAMPLE_RATE_CONF

pdm_conf: Reg<PDM_CONF_SPEC>

0xb4 - I2S_PDM_CONF

pdm_freq_conf: Reg<PDM_FREQ_CONF_SPEC>

0xb8 - I2S_PDM_FREQ_CONF

state: Reg<STATE_SPEC>

0xbc - I2S_STATE

date: Reg<DATE_SPEC>

0xfc - I2S_DATE

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