#[doc = "Register `CNTL` reader"]
pub struct R(crate::R<CNTL_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CNTL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::convert::From<crate::R<CNTL_SPEC>> for R {
fn from(reader: crate::R<CNTL_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CNTL` writer"]
pub struct W(crate::W<CNTL_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CNTL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl core::convert::From<crate::W<CNTL_SPEC>> for W {
fn from(writer: crate::W<CNTL_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `FORCE_PU` reader - Force RTC power up"]
pub struct FORCE_PU_R(crate::FieldReader<bool, bool>);
impl FORCE_PU_R {
pub(crate) fn new(bits: bool) -> Self {
FORCE_PU_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for FORCE_PU_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `FORCE_PU` writer - Force RTC power up"]
pub struct FORCE_PU_W<'a> {
w: &'a mut W,
}
impl<'a> FORCE_PU_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
self.w
}
}
#[doc = "Field `FORCE_PD` reader - Force RTC power down (decrease voltage to 0.8V or lower)"]
pub struct FORCE_PD_R(crate::FieldReader<bool, bool>);
impl FORCE_PD_R {
pub(crate) fn new(bits: bool) -> Self {
FORCE_PD_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for FORCE_PD_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `FORCE_PD` writer - Force RTC power down (decrease voltage to 0.8V or lower)"]
pub struct FORCE_PD_W<'a> {
w: &'a mut W,
}
impl<'a> FORCE_PD_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30);
self.w
}
}
#[doc = "Field `FORCE_DBOOST_PU` reader - Force DBOOST power up"]
pub struct FORCE_DBOOST_PU_R(crate::FieldReader<bool, bool>);
impl FORCE_DBOOST_PU_R {
pub(crate) fn new(bits: bool) -> Self {
FORCE_DBOOST_PU_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for FORCE_DBOOST_PU_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `FORCE_DBOOST_PU` writer - Force DBOOST power up"]
pub struct FORCE_DBOOST_PU_W<'a> {
w: &'a mut W,
}
impl<'a> FORCE_DBOOST_PU_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29);
self.w
}
}
#[doc = "Field `FORCE_DBOOST_PD` reader - Force DBOOST power down"]
pub struct FORCE_DBOOST_PD_R(crate::FieldReader<bool, bool>);
impl FORCE_DBOOST_PD_R {
pub(crate) fn new(bits: bool) -> Self {
FORCE_DBOOST_PD_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for FORCE_DBOOST_PD_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `FORCE_DBOOST_PD` writer - Force DBOOST power down"]
pub struct FORCE_DBOOST_PD_W<'a> {
w: &'a mut W,
}
impl<'a> FORCE_DBOOST_PD_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28);
self.w
}
}
#[doc = "RTC DBIAS during wakeup\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum DBIAS_WAK_A {
#[doc = "0: Core voltage 0.90V"]
BIAS_0V90 = 0,
#[doc = "1: Core voltage 0.95V"]
BIAS_0V95 = 1,
#[doc = "2: Core voltage 1.00V"]
BIAS_1V00 = 2,
#[doc = "3: Core voltage 1.05V"]
BIAS_1V05 = 3,
#[doc = "4: Core voltage 1.10V"]
BIAS_1V10 = 4,
#[doc = "5: Core voltage 1.15V"]
BIAS_1V15 = 5,
#[doc = "6: Core voltage 1.20V"]
BIAS_1V20 = 6,
#[doc = "7: Core voltage 1.25V"]
BIAS_1V25 = 7,
}
impl From<DBIAS_WAK_A> for u8 {
#[inline(always)]
fn from(variant: DBIAS_WAK_A) -> Self {
variant as _
}
}
#[doc = "Field `DBIAS_WAK` reader - RTC DBIAS during wakeup"]
pub struct DBIAS_WAK_R(crate::FieldReader<u8, DBIAS_WAK_A>);
impl DBIAS_WAK_R {
pub(crate) fn new(bits: u8) -> Self {
DBIAS_WAK_R(crate::FieldReader::new(bits))
}
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> DBIAS_WAK_A {
match self.bits {
0 => DBIAS_WAK_A::BIAS_0V90,
1 => DBIAS_WAK_A::BIAS_0V95,
2 => DBIAS_WAK_A::BIAS_1V00,
3 => DBIAS_WAK_A::BIAS_1V05,
4 => DBIAS_WAK_A::BIAS_1V10,
5 => DBIAS_WAK_A::BIAS_1V15,
6 => DBIAS_WAK_A::BIAS_1V20,
7 => DBIAS_WAK_A::BIAS_1V25,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `BIAS_0V90`"]
#[inline(always)]
pub fn is_bias_0v90(&self) -> bool {
**self == DBIAS_WAK_A::BIAS_0V90
}
#[doc = "Checks if the value of the field is `BIAS_0V95`"]
#[inline(always)]
pub fn is_bias_0v95(&self) -> bool {
**self == DBIAS_WAK_A::BIAS_0V95
}
#[doc = "Checks if the value of the field is `BIAS_1V00`"]
#[inline(always)]
pub fn is_bias_1v00(&self) -> bool {
**self == DBIAS_WAK_A::BIAS_1V00
}
#[doc = "Checks if the value of the field is `BIAS_1V05`"]
#[inline(always)]
pub fn is_bias_1v05(&self) -> bool {
**self == DBIAS_WAK_A::BIAS_1V05
}
#[doc = "Checks if the value of the field is `BIAS_1V10`"]
#[inline(always)]
pub fn is_bias_1v10(&self) -> bool {
**self == DBIAS_WAK_A::BIAS_1V10
}
#[doc = "Checks if the value of the field is `BIAS_1V15`"]
#[inline(always)]
pub fn is_bias_1v15(&self) -> bool {
**self == DBIAS_WAK_A::BIAS_1V15
}
#[doc = "Checks if the value of the field is `BIAS_1V20`"]
#[inline(always)]
pub fn is_bias_1v20(&self) -> bool {
**self == DBIAS_WAK_A::BIAS_1V20
}
#[doc = "Checks if the value of the field is `BIAS_1V25`"]
#[inline(always)]
pub fn is_bias_1v25(&self) -> bool {
**self == DBIAS_WAK_A::BIAS_1V25
}
}
impl core::ops::Deref for DBIAS_WAK_R {
type Target = crate::FieldReader<u8, DBIAS_WAK_A>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `DBIAS_WAK` writer - RTC DBIAS during wakeup"]
pub struct DBIAS_WAK_W<'a> {
w: &'a mut W,
}
impl<'a> DBIAS_WAK_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: DBIAS_WAK_A) -> &'a mut W {
self.bits(variant.into())
}
#[doc = "Core voltage 0.90V"]
#[inline(always)]
pub fn bias_0v90(self) -> &'a mut W {
self.variant(DBIAS_WAK_A::BIAS_0V90)
}
#[doc = "Core voltage 0.95V"]
#[inline(always)]
pub fn bias_0v95(self) -> &'a mut W {
self.variant(DBIAS_WAK_A::BIAS_0V95)
}
#[doc = "Core voltage 1.00V"]
#[inline(always)]
pub fn bias_1v00(self) -> &'a mut W {
self.variant(DBIAS_WAK_A::BIAS_1V00)
}
#[doc = "Core voltage 1.05V"]
#[inline(always)]
pub fn bias_1v05(self) -> &'a mut W {
self.variant(DBIAS_WAK_A::BIAS_1V05)
}
#[doc = "Core voltage 1.10V"]
#[inline(always)]
pub fn bias_1v10(self) -> &'a mut W {
self.variant(DBIAS_WAK_A::BIAS_1V10)
}
#[doc = "Core voltage 1.15V"]
#[inline(always)]
pub fn bias_1v15(self) -> &'a mut W {
self.variant(DBIAS_WAK_A::BIAS_1V15)
}
#[doc = "Core voltage 1.20V"]
#[inline(always)]
pub fn bias_1v20(self) -> &'a mut W {
self.variant(DBIAS_WAK_A::BIAS_1V20)
}
#[doc = "Core voltage 1.25V"]
#[inline(always)]
pub fn bias_1v25(self) -> &'a mut W {
self.variant(DBIAS_WAK_A::BIAS_1V25)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x07 << 25)) | (((value as u32) & 0x07) << 25);
self.w
}
}
#[doc = "RTC DBIAS during sleep"]
pub type DBIAS_SLP_A = DBIAS_WAK_A;
#[doc = "Field `DBIAS_SLP` reader - RTC DBIAS during sleep"]
pub type DBIAS_SLP_R = DBIAS_WAK_R;
#[doc = "Field `DBIAS_SLP` writer - RTC DBIAS during sleep"]
pub struct DBIAS_SLP_W<'a> {
w: &'a mut W,
}
impl<'a> DBIAS_SLP_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: DBIAS_SLP_A) -> &'a mut W {
self.bits(variant.into())
}
#[doc = "Core voltage 0.90V"]
#[inline(always)]
pub fn bias_0v90(self) -> &'a mut W {
self.variant(DBIAS_SLP_A::BIAS_0V90)
}
#[doc = "Core voltage 0.95V"]
#[inline(always)]
pub fn bias_0v95(self) -> &'a mut W {
self.variant(DBIAS_SLP_A::BIAS_0V95)
}
#[doc = "Core voltage 1.00V"]
#[inline(always)]
pub fn bias_1v00(self) -> &'a mut W {
self.variant(DBIAS_SLP_A::BIAS_1V00)
}
#[doc = "Core voltage 1.05V"]
#[inline(always)]
pub fn bias_1v05(self) -> &'a mut W {
self.variant(DBIAS_SLP_A::BIAS_1V05)
}
#[doc = "Core voltage 1.10V"]
#[inline(always)]
pub fn bias_1v10(self) -> &'a mut W {
self.variant(DBIAS_SLP_A::BIAS_1V10)
}
#[doc = "Core voltage 1.15V"]
#[inline(always)]
pub fn bias_1v15(self) -> &'a mut W {
self.variant(DBIAS_SLP_A::BIAS_1V15)
}
#[doc = "Core voltage 1.20V"]
#[inline(always)]
pub fn bias_1v20(self) -> &'a mut W {
self.variant(DBIAS_SLP_A::BIAS_1V20)
}
#[doc = "Core voltage 1.25V"]
#[inline(always)]
pub fn bias_1v25(self) -> &'a mut W {
self.variant(DBIAS_SLP_A::BIAS_1V25)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x07 << 22)) | (((value as u32) & 0x07) << 22);
self.w
}
}
#[doc = "Field `SCK_DCAP` reader - 150kHz oscillator tuning"]
pub struct SCK_DCAP_R(crate::FieldReader<u8, u8>);
impl SCK_DCAP_R {
pub(crate) fn new(bits: u8) -> Self {
SCK_DCAP_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for SCK_DCAP_R {
type Target = crate::FieldReader<u8, u8>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `SCK_DCAP` writer - 150kHz oscillator tuning"]
pub struct SCK_DCAP_W<'a> {
w: &'a mut W,
}
impl<'a> SCK_DCAP_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0xff << 14)) | (((value as u32) & 0xff) << 14);
self.w
}
}
#[doc = "DBIAS during wakeup"]
pub type DIG_DBIAS_WAK_A = DBIAS_WAK_A;
#[doc = "Field `DIG_DBIAS_WAK` reader - DBIAS during wakeup"]
pub type DIG_DBIAS_WAK_R = DBIAS_WAK_R;
#[doc = "Field `DIG_DBIAS_WAK` writer - DBIAS during wakeup"]
pub struct DIG_DBIAS_WAK_W<'a> {
w: &'a mut W,
}
impl<'a> DIG_DBIAS_WAK_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: DIG_DBIAS_WAK_A) -> &'a mut W {
self.bits(variant.into())
}
#[doc = "Core voltage 0.90V"]
#[inline(always)]
pub fn bias_0v90(self) -> &'a mut W {
self.variant(DIG_DBIAS_WAK_A::BIAS_0V90)
}
#[doc = "Core voltage 0.95V"]
#[inline(always)]
pub fn bias_0v95(self) -> &'a mut W {
self.variant(DIG_DBIAS_WAK_A::BIAS_0V95)
}
#[doc = "Core voltage 1.00V"]
#[inline(always)]
pub fn bias_1v00(self) -> &'a mut W {
self.variant(DIG_DBIAS_WAK_A::BIAS_1V00)
}
#[doc = "Core voltage 1.05V"]
#[inline(always)]
pub fn bias_1v05(self) -> &'a mut W {
self.variant(DIG_DBIAS_WAK_A::BIAS_1V05)
}
#[doc = "Core voltage 1.10V"]
#[inline(always)]
pub fn bias_1v10(self) -> &'a mut W {
self.variant(DIG_DBIAS_WAK_A::BIAS_1V10)
}
#[doc = "Core voltage 1.15V"]
#[inline(always)]
pub fn bias_1v15(self) -> &'a mut W {
self.variant(DIG_DBIAS_WAK_A::BIAS_1V15)
}
#[doc = "Core voltage 1.20V"]
#[inline(always)]
pub fn bias_1v20(self) -> &'a mut W {
self.variant(DIG_DBIAS_WAK_A::BIAS_1V20)
}
#[doc = "Core voltage 1.25V"]
#[inline(always)]
pub fn bias_1v25(self) -> &'a mut W {
self.variant(DIG_DBIAS_WAK_A::BIAS_1V25)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x07 << 11)) | (((value as u32) & 0x07) << 11);
self.w
}
}
#[doc = "DBIAS during wakeup"]
pub type DIG_DBIAS_SLP_A = DBIAS_WAK_A;
#[doc = "Field `DIG_DBIAS_SLP` reader - DBIAS during wakeup"]
pub type DIG_DBIAS_SLP_R = DBIAS_WAK_R;
#[doc = "Field `DIG_DBIAS_SLP` writer - DBIAS during wakeup"]
pub struct DIG_DBIAS_SLP_W<'a> {
w: &'a mut W,
}
impl<'a> DIG_DBIAS_SLP_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: DIG_DBIAS_SLP_A) -> &'a mut W {
self.bits(variant.into())
}
#[doc = "Core voltage 0.90V"]
#[inline(always)]
pub fn bias_0v90(self) -> &'a mut W {
self.variant(DIG_DBIAS_SLP_A::BIAS_0V90)
}
#[doc = "Core voltage 0.95V"]
#[inline(always)]
pub fn bias_0v95(self) -> &'a mut W {
self.variant(DIG_DBIAS_SLP_A::BIAS_0V95)
}
#[doc = "Core voltage 1.00V"]
#[inline(always)]
pub fn bias_1v00(self) -> &'a mut W {
self.variant(DIG_DBIAS_SLP_A::BIAS_1V00)
}
#[doc = "Core voltage 1.05V"]
#[inline(always)]
pub fn bias_1v05(self) -> &'a mut W {
self.variant(DIG_DBIAS_SLP_A::BIAS_1V05)
}
#[doc = "Core voltage 1.10V"]
#[inline(always)]
pub fn bias_1v10(self) -> &'a mut W {
self.variant(DIG_DBIAS_SLP_A::BIAS_1V10)
}
#[doc = "Core voltage 1.15V"]
#[inline(always)]
pub fn bias_1v15(self) -> &'a mut W {
self.variant(DIG_DBIAS_SLP_A::BIAS_1V15)
}
#[doc = "Core voltage 1.20V"]
#[inline(always)]
pub fn bias_1v20(self) -> &'a mut W {
self.variant(DIG_DBIAS_SLP_A::BIAS_1V20)
}
#[doc = "Core voltage 1.25V"]
#[inline(always)]
pub fn bias_1v25(self) -> &'a mut W {
self.variant(DIG_DBIAS_SLP_A::BIAS_1V25)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x07 << 8)) | (((value as u32) & 0x07) << 8);
self.w
}
}
#[doc = "Field `SCK_DCAP_FORCE` reader - 150kHz tuning force"]
pub struct SCK_DCAP_FORCE_R(crate::FieldReader<bool, bool>);
impl SCK_DCAP_FORCE_R {
pub(crate) fn new(bits: bool) -> Self {
SCK_DCAP_FORCE_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for SCK_DCAP_FORCE_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `SCK_DCAP_FORCE` writer - 150kHz tuning force"]
pub struct SCK_DCAP_FORCE_W<'a> {
w: &'a mut W,
}
impl<'a> SCK_DCAP_FORCE_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
self.w
}
}
impl R {
#[doc = "Bit 31 - Force RTC power up"]
#[inline(always)]
pub fn force_pu(&self) -> FORCE_PU_R {
FORCE_PU_R::new(((self.bits >> 31) & 0x01) != 0)
}
#[doc = "Bit 30 - Force RTC power down (decrease voltage to 0.8V or lower)"]
#[inline(always)]
pub fn force_pd(&self) -> FORCE_PD_R {
FORCE_PD_R::new(((self.bits >> 30) & 0x01) != 0)
}
#[doc = "Bit 29 - Force DBOOST power up"]
#[inline(always)]
pub fn force_dboost_pu(&self) -> FORCE_DBOOST_PU_R {
FORCE_DBOOST_PU_R::new(((self.bits >> 29) & 0x01) != 0)
}
#[doc = "Bit 28 - Force DBOOST power down"]
#[inline(always)]
pub fn force_dboost_pd(&self) -> FORCE_DBOOST_PD_R {
FORCE_DBOOST_PD_R::new(((self.bits >> 28) & 0x01) != 0)
}
#[doc = "Bits 25:27 - RTC DBIAS during wakeup"]
#[inline(always)]
pub fn dbias_wak(&self) -> DBIAS_WAK_R {
DBIAS_WAK_R::new(((self.bits >> 25) & 0x07) as u8)
}
#[doc = "Bits 22:24 - RTC DBIAS during sleep"]
#[inline(always)]
pub fn dbias_slp(&self) -> DBIAS_SLP_R {
DBIAS_SLP_R::new(((self.bits >> 22) & 0x07) as u8)
}
#[doc = "Bits 14:21 - 150kHz oscillator tuning"]
#[inline(always)]
pub fn sck_dcap(&self) -> SCK_DCAP_R {
SCK_DCAP_R::new(((self.bits >> 14) & 0xff) as u8)
}
#[doc = "Bits 11:13 - DBIAS during wakeup"]
#[inline(always)]
pub fn dig_dbias_wak(&self) -> DIG_DBIAS_WAK_R {
DIG_DBIAS_WAK_R::new(((self.bits >> 11) & 0x07) as u8)
}
#[doc = "Bits 8:10 - DBIAS during wakeup"]
#[inline(always)]
pub fn dig_dbias_slp(&self) -> DIG_DBIAS_SLP_R {
DIG_DBIAS_SLP_R::new(((self.bits >> 8) & 0x07) as u8)
}
#[doc = "Bit 7 - 150kHz tuning force"]
#[inline(always)]
pub fn sck_dcap_force(&self) -> SCK_DCAP_FORCE_R {
SCK_DCAP_FORCE_R::new(((self.bits >> 7) & 0x01) != 0)
}
}
impl W {
#[doc = "Bit 31 - Force RTC power up"]
#[inline(always)]
pub fn force_pu(&mut self) -> FORCE_PU_W {
FORCE_PU_W { w: self }
}
#[doc = "Bit 30 - Force RTC power down (decrease voltage to 0.8V or lower)"]
#[inline(always)]
pub fn force_pd(&mut self) -> FORCE_PD_W {
FORCE_PD_W { w: self }
}
#[doc = "Bit 29 - Force DBOOST power up"]
#[inline(always)]
pub fn force_dboost_pu(&mut self) -> FORCE_DBOOST_PU_W {
FORCE_DBOOST_PU_W { w: self }
}
#[doc = "Bit 28 - Force DBOOST power down"]
#[inline(always)]
pub fn force_dboost_pd(&mut self) -> FORCE_DBOOST_PD_W {
FORCE_DBOOST_PD_W { w: self }
}
#[doc = "Bits 25:27 - RTC DBIAS during wakeup"]
#[inline(always)]
pub fn dbias_wak(&mut self) -> DBIAS_WAK_W {
DBIAS_WAK_W { w: self }
}
#[doc = "Bits 22:24 - RTC DBIAS during sleep"]
#[inline(always)]
pub fn dbias_slp(&mut self) -> DBIAS_SLP_W {
DBIAS_SLP_W { w: self }
}
#[doc = "Bits 14:21 - 150kHz oscillator tuning"]
#[inline(always)]
pub fn sck_dcap(&mut self) -> SCK_DCAP_W {
SCK_DCAP_W { w: self }
}
#[doc = "Bits 11:13 - DBIAS during wakeup"]
#[inline(always)]
pub fn dig_dbias_wak(&mut self) -> DIG_DBIAS_WAK_W {
DIG_DBIAS_WAK_W { w: self }
}
#[doc = "Bits 8:10 - DBIAS during wakeup"]
#[inline(always)]
pub fn dig_dbias_slp(&mut self) -> DIG_DBIAS_SLP_W {
DIG_DBIAS_SLP_W { w: self }
}
#[doc = "Bit 7 - 150kHz tuning force"]
#[inline(always)]
pub fn sck_dcap_force(&mut self) -> SCK_DCAP_FORCE_W {
SCK_DCAP_FORCE_W { w: self }
}
#[doc = "Writes raw bits to the register."]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "RTC Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cntl](index.html) module"]
pub struct CNTL_SPEC;
impl crate::RegisterSpec for CNTL_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cntl::R](R) reader structure"]
impl crate::Readable for CNTL_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cntl::W](W) writer structure"]
impl crate::Writable for CNTL_SPEC {
type Writer = W;
}
#[doc = "`reset()` method sets CNTL to value 0"]
impl crate::Resettable for CNTL_SPEC {
#[inline(always)]
fn reset_value() -> Self::Ux {
0
}
}