#[cfg(any(esp32, esp32s3))]
use core::arch::asm;
use esp_idf_sys::*;
pub const CORES: u32 = SOC_CPU_CORES_NUM;
#[repr(C)]
#[derive(Copy, Clone, Eq, PartialEq, Debug)]
pub enum Core {
Core0 = 0, #[cfg(any(esp32, esp32s3))]
Core1 = 1, }
impl Core {
#[inline(always)]
#[link_section = ".iram1.cpu_core"]
pub fn is_active(&self) -> bool {
*self == core()
}
}
impl From<Core> for i32 {
fn from(core: Core) -> Self {
core as _
}
}
impl From<i32> for Core {
fn from(core: i32) -> Self {
match core {
0 => Core::Core0,
#[cfg(any(esp32, esp32s3))]
1 => Core::Core1,
_ => panic!(),
}
}
}
#[inline(always)]
#[link_section = ".iram1.cpu_core"]
pub fn core() -> Core {
#[cfg(any(esp32c3, esp32s2))]
let core = 0;
#[allow(unused_assignments)]
#[cfg(any(esp32, esp32s3))]
let mut core = 0;
#[cfg(any(esp32, esp32s3))]
unsafe {
asm!("rsr.prid {0}", "extui {0},{0},13,1", out(reg) core);
}
match core {
0 => Core::Core0,
#[cfg(any(esp32, esp32s3))]
1 => Core::Core1,
other => panic!("Unknown core: {}", other),
}
}