esp-hal 1.2.0

use enumset::EnumSet;
use portable_atomic::Ordering;

use crate::{
    RegisterToggle,
    asynch::AtomicWaker,
    dma::{
        BurstConfig,
        DmaChannel,
        DmaRxChannel,
        DmaRxInterrupt,
        DmaTxChannel,
        DmaTxInterrupt,
        InterruptAccess,
        RegisterAccess,
        RxRegisterAccess,
        TxRegisterAccess,
    },
    interrupt::InterruptHandler,
    peripherals::Interrupt,
    system::PeripheralGuard,
};

/// Immutable per-channel metadata.
#[doc(hidden)]
pub struct ChannelInfo {
    pub(crate) peripheral_interrupt: Interrupt,

    pub(crate) async_handler: InterruptHandler,

    /// Peripheral IDs this channel can serve. An empty slice means no runtime check is needed.
    pub(crate) compatible_peripherals: &'static [u8],
}

/// Mutable per-channel runtime state (wakers and async-mode flags).
pub(crate) struct ChannelState {
    /// Async waker for the TX (out) half of this channel.
    pub(crate) tx_waker: AtomicWaker,

    /// Async waker for the RX (in) half of this channel.
    pub(crate) rx_waker: AtomicWaker,

    /// Whether the TX half is currently in async mode.
    pub(crate) tx_async_flag: portable_atomic::AtomicBool,

    /// Whether the RX half is currently in async mode.
    pub(crate) rx_async_flag: portable_atomic::AtomicBool,
}

pub(super) type I2sRegisterBlock = crate::pac::i2s0::RegisterBlock;

/// The RX half of an arbitrary I2S DMA channel.
#[derive(Debug)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub struct I2sDmaRxChannel<'d>(pub(crate) I2sDmaChannel<'d>);

impl I2sDmaRxChannel<'_> {
    fn regs(&self) -> &I2sRegisterBlock {
        self.0.register_block()
    }
}

impl crate::private::Sealed for I2sDmaRxChannel<'_> {}
impl DmaRxChannel for I2sDmaRxChannel<'_> {}

/// The TX half of an arbitrary I2S DMA channel.
#[derive(Debug)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub struct I2sDmaTxChannel<'d>(pub(crate) I2sDmaChannel<'d>);

impl I2sDmaTxChannel<'_> {
    fn regs(&self) -> &I2sRegisterBlock {
        self.0.register_block()
    }
}

impl crate::private::Sealed for I2sDmaTxChannel<'_> {}
impl DmaTxChannel for I2sDmaTxChannel<'_> {}

impl RegisterAccess for I2sDmaTxChannel<'_> {
    #[allow(private_interfaces)]
    fn enable(&self) -> Option<PeripheralGuard> {
        None
    }

    fn reset(&self) {
        self.regs().lc_conf().toggle(|w, bit| w.out_rst().bit(bit));
    }

    fn set_burst_mode(&self, burst_mode: BurstConfig) {
        self.regs()
            .lc_conf()
            .modify(|_, w| w.out_data_burst_en().bit(burst_mode.is_burst_enabled()));
    }

    fn set_descr_burst_mode(&self, burst_mode: bool) {
        self.regs()
            .lc_conf()
            .modify(|_, w| w.outdscr_burst_en().bit(burst_mode));
    }

    fn set_link_addr(&self, address: u32) {
        self.regs()
            .out_link()
            .modify(|_, w| unsafe { w.outlink_addr().bits(address) });
    }

    fn start(&self) {
        self.regs()
            .out_link()
            .modify(|_, w| w.outlink_start().set_bit());
    }

    fn stop(&self) {
        self.regs()
            .out_link()
            .modify(|_, w| w.outlink_stop().set_bit());
    }

    fn restart(&self) {
        self.regs()
            .out_link()
            .modify(|_, w| w.outlink_restart().set_bit());
    }

    fn set_check_owner(&self, check_owner: Option<bool>) {
        self.regs()
            .lc_conf()
            .modify(|_, w| w.check_owner().bit(check_owner.unwrap_or(true)));
    }

    #[cfg(dma_ext_mem_configurable_block_size)]
    fn set_ext_mem_block_size(&self, size: crate::dma::DmaExtMemBKSize) {
        self.regs()
            .lc_conf()
            .modify(|_, w| unsafe { w.ext_mem_bk_size().bits(size as u8) });
    }

    #[cfg(dma_can_access_psram)]
    fn can_access_psram(&self) -> bool {
        matches!(self.0, I2sDmaChannel(any::Inner::I2s0(_)))
    }

    fn compatible_peripherals(&self) -> &[u8] {
        self.0.info().compatible_peripherals
    }
}

impl TxRegisterAccess for I2sDmaTxChannel<'_> {
    fn is_fifo_empty(&self) -> bool {
        cfg_select! {
            esp32 => self.regs().lc_state0().read().bits() & 0x80000000 != 0,
            _ => self.regs().lc_state0().read().out_empty().bit_is_set(),
        }
    }

    fn set_auto_write_back(&self, enable: bool) {
        self.regs()
            .lc_conf()
            .modify(|_, w| w.out_auto_wrback().bit(enable));
    }

    fn last_dscr_address(&self) -> usize {
        self.regs()
            .out_eof_des_addr()
            .read()
            .out_eof_des_addr()
            .bits() as usize
    }

    fn peripheral_interrupt(&self) -> Option<Interrupt> {
        Some(self.0.info().peripheral_interrupt)
    }

    fn async_handler(&self) -> Option<InterruptHandler> {
        Some(self.0.info().async_handler)
    }
}

impl InterruptAccess<DmaTxInterrupt> for I2sDmaTxChannel<'_> {
    fn enable_listen(&self, interrupts: EnumSet<DmaTxInterrupt>, enable: bool) {
        self.regs().int_ena().modify(|_, w| {
            for interrupt in interrupts {
                match interrupt {
                    DmaTxInterrupt::TotalEof => w.out_total_eof().bit(enable),
                    DmaTxInterrupt::DescriptorError => w.out_dscr_err().bit(enable),
                    DmaTxInterrupt::Eof => w.out_eof().bit(enable),
                    DmaTxInterrupt::Done => w.out_done().bit(enable),
                };
            }
            w
        });
    }

    fn is_listening(&self) -> EnumSet<DmaTxInterrupt> {
        let mut result = EnumSet::new();

        let int_ena = self.regs().int_ena().read();
        if int_ena.out_total_eof().bit_is_set() {
            result |= DmaTxInterrupt::TotalEof;
        }
        if int_ena.out_dscr_err().bit_is_set() {
            result |= DmaTxInterrupt::DescriptorError;
        }
        if int_ena.out_eof().bit_is_set() {
            result |= DmaTxInterrupt::Eof;
        }
        if int_ena.out_done().bit_is_set() {
            result |= DmaTxInterrupt::Done;
        }

        result
    }

    fn pending_interrupts(&self) -> EnumSet<DmaTxInterrupt> {
        let mut result = EnumSet::new();

        let int_raw = self.regs().int_raw().read();
        if int_raw.out_total_eof().bit_is_set() {
            result |= DmaTxInterrupt::TotalEof;
        }
        if int_raw.out_dscr_err().bit_is_set() {
            result |= DmaTxInterrupt::DescriptorError;
        }
        if int_raw.out_eof().bit_is_set() {
            result |= DmaTxInterrupt::Eof;
        }
        if int_raw.out_done().bit_is_set() {
            result |= DmaTxInterrupt::Done;
        }

        result
    }

    fn clear(&self, interrupts: impl Into<EnumSet<DmaTxInterrupt>>) {
        self.regs().int_clr().write(|w| {
            for interrupt in interrupts.into() {
                match interrupt {
                    DmaTxInterrupt::TotalEof => w.out_total_eof().clear_bit_by_one(),
                    DmaTxInterrupt::DescriptorError => w.out_dscr_err().clear_bit_by_one(),
                    DmaTxInterrupt::Eof => w.out_eof().clear_bit_by_one(),
                    DmaTxInterrupt::Done => w.out_done().clear_bit_by_one(),
                };
            }
            w
        });
    }

    fn waker(&self) -> &'static AtomicWaker {
        &self.0.state().tx_waker
    }

    fn is_async(&self) -> bool {
        self.0.state().tx_async_flag.load(Ordering::Relaxed)
    }

    fn set_async(&self, is_async: bool) {
        self.0
            .state()
            .tx_async_flag
            .store(is_async, Ordering::Relaxed);
    }
}

impl RegisterAccess for I2sDmaRxChannel<'_> {
    #[allow(private_interfaces)]
    fn enable(&self) -> Option<PeripheralGuard> {
        None
    }

    fn reset(&self) {
        self.regs().lc_conf().toggle(|w, bit| w.in_rst().bit(bit));
    }

    fn set_burst_mode(&self, _burst_mode: BurstConfig) {}

    fn set_descr_burst_mode(&self, burst_mode: bool) {
        self.regs()
            .lc_conf()
            .modify(|_, w| w.indscr_burst_en().bit(burst_mode));
    }

    fn set_link_addr(&self, address: u32) {
        self.regs()
            .in_link()
            .modify(|_, w| unsafe { w.inlink_addr().bits(address) });
    }

    fn start(&self) {
        self.regs()
            .in_link()
            .modify(|_, w| w.inlink_start().set_bit());
    }

    fn stop(&self) {
        self.regs()
            .in_link()
            .modify(|_, w| w.inlink_stop().set_bit());
    }

    fn restart(&self) {
        self.regs()
            .in_link()
            .modify(|_, w| w.inlink_restart().set_bit());
    }

    fn set_check_owner(&self, check_owner: Option<bool>) {
        self.regs()
            .lc_conf()
            .modify(|_, w| w.check_owner().bit(check_owner.unwrap_or(true)));
    }

    #[cfg(dma_ext_mem_configurable_block_size)]
    fn set_ext_mem_block_size(&self, size: crate::dma::DmaExtMemBKSize) {
        self.regs()
            .lc_conf()
            .modify(|_, w| unsafe { w.ext_mem_bk_size().bits(size as u8) });
    }

    #[cfg(dma_can_access_psram)]
    fn can_access_psram(&self) -> bool {
        matches!(self.0, I2sDmaChannel(any::Inner::I2s0(_)))
    }

    fn compatible_peripherals(&self) -> &[u8] {
        self.0.info().compatible_peripherals
    }
}

impl RxRegisterAccess for I2sDmaRxChannel<'_> {
    #[cfg(dma_supports_mem2mem)]
    fn set_mem2mem_mode(&self, en: bool) {
        self.regs()
            .lc_conf()
            .modify(|_, w| w.mem_trans_en().bit(en));
    }

    fn peripheral_interrupt(&self) -> Option<Interrupt> {
        Some(self.0.info().peripheral_interrupt)
    }

    fn async_handler(&self) -> Option<InterruptHandler> {
        Some(self.0.info().async_handler)
    }
}

impl InterruptAccess<DmaRxInterrupt> for I2sDmaRxChannel<'_> {
    fn enable_listen(&self, interrupts: EnumSet<DmaRxInterrupt>, enable: bool) {
        self.regs().int_ena().modify(|_, w| {
            for interrupt in interrupts {
                match interrupt {
                    DmaRxInterrupt::SuccessfulEof => w.in_suc_eof().bit(enable),
                    DmaRxInterrupt::ErrorEof => w.in_err_eof().bit(enable),
                    DmaRxInterrupt::DescriptorError => w.in_dscr_err().bit(enable),
                    DmaRxInterrupt::DescriptorEmpty => w.in_dscr_empty().bit(enable),
                    DmaRxInterrupt::Done => w.in_done().bit(enable),
                };
            }
            w
        });
    }

    fn is_listening(&self) -> EnumSet<DmaRxInterrupt> {
        let mut result = EnumSet::new();

        let int_ena = self.regs().int_ena().read();
        if int_ena.in_dscr_err().bit_is_set() {
            result |= DmaRxInterrupt::DescriptorError;
        }
        if int_ena.in_dscr_empty().bit_is_set() {
            result |= DmaRxInterrupt::DescriptorEmpty;
        }
        if int_ena.in_suc_eof().bit_is_set() {
            result |= DmaRxInterrupt::SuccessfulEof;
        }
        if int_ena.in_err_eof().bit_is_set() {
            result |= DmaRxInterrupt::ErrorEof;
        }
        if int_ena.in_done().bit_is_set() {
            result |= DmaRxInterrupt::Done;
        }

        result
    }

    fn pending_interrupts(&self) -> EnumSet<DmaRxInterrupt> {
        let mut result = EnumSet::new();

        let int_raw = self.regs().int_raw().read();
        if int_raw.in_dscr_err().bit_is_set() {
            result |= DmaRxInterrupt::DescriptorError;
        }
        if int_raw.in_dscr_empty().bit_is_set() {
            result |= DmaRxInterrupt::DescriptorEmpty;
        }
        if int_raw.in_suc_eof().bit_is_set() {
            result |= DmaRxInterrupt::SuccessfulEof;
        }
        if int_raw.in_err_eof().bit_is_set() {
            result |= DmaRxInterrupt::ErrorEof;
        }
        if int_raw.in_done().bit_is_set() {
            result |= DmaRxInterrupt::Done;
        }

        result
    }

    fn clear(&self, interrupts: impl Into<EnumSet<DmaRxInterrupt>>) {
        self.regs().int_clr().write(|w| {
            for interrupt in interrupts.into() {
                match interrupt {
                    DmaRxInterrupt::SuccessfulEof => w.in_suc_eof().clear_bit_by_one(),
                    DmaRxInterrupt::ErrorEof => w.in_err_eof().clear_bit_by_one(),
                    DmaRxInterrupt::DescriptorError => w.in_dscr_err().clear_bit_by_one(),
                    DmaRxInterrupt::DescriptorEmpty => w.in_dscr_empty().clear_bit_by_one(),
                    DmaRxInterrupt::Done => w.in_done().clear_bit_by_one(),
                };
            }
            w
        });
    }

    fn waker(&self) -> &'static AtomicWaker {
        &self.0.state().rx_waker
    }

    fn is_async(&self) -> bool {
        self.0.state().rx_async_flag.load(Ordering::Relaxed)
    }

    fn set_async(&self, is_async: bool) {
        self.0
            .state()
            .rx_async_flag
            .store(is_async, Ordering::Relaxed);
    }
}

crate::any_peripheral! {
    /// An I2S-compatible type-erased DMA channel.
    pub peripheral I2sDmaChannel<'d> {
        #[cfg(soc_has_i2s0)]
        I2s0(DMA_I2S0<'d>),
        #[cfg(soc_has_i2s1)]
        I2s1(DMA_I2S1<'d>),
    }
}

impl<'d> DmaChannel for I2sDmaChannel<'d> {
    type Rx = I2sDmaRxChannel<'d>;
    type Tx = I2sDmaTxChannel<'d>;

    unsafe fn split_internal(self, _: crate::private::Internal) -> (Self::Rx, Self::Tx) {
        (
            I2sDmaRxChannel(unsafe { self.clone_unchecked() }),
            I2sDmaTxChannel(self),
        )
    }
}

impl I2sDmaChannel<'_> {
    delegate::delegate! {
        to match &self.0 {
            #[cfg(soc_has_i2s0)]
            any::Inner::I2s0(channel) => channel,
            #[cfg(soc_has_i2s1)]
            any::Inner::I2s1(channel) => channel,
        } {
            fn register_block(&self) -> &I2sRegisterBlock;
            fn info(&self) -> &'static ChannelInfo;
            fn state(&self) -> &'static ChannelState;
        }
    }
}

// Convert erased channel into erased TX/RX half structs
impl<'d> From<I2sDmaChannel<'d>> for I2sDmaRxChannel<'d> {
    fn from(this: I2sDmaChannel<'d>) -> I2sDmaRxChannel<'d> {
        I2sDmaRxChannel(this)
    }
}

impl<'d> From<I2sDmaChannel<'d>> for I2sDmaTxChannel<'d> {
    fn from(this: I2sDmaChannel<'d>) -> I2sDmaTxChannel<'d> {
        I2sDmaTxChannel(this)
    }
}

for_each_dma_channel_peri_pair! {
    ("I2S_DMA", $dma_peri:ident, $peri:ident) => {
        use crate::peripherals::$dma_peri;
        impl $dma_peri<'_> {
            pub(super) fn info(&self) -> &'static ChannelInfo {
                #[crate::handler(priority = crate::interrupt::Priority::max())]
                fn interrupt_handler() {
                    crate::dma::asynch::handle_in_interrupt::<$dma_peri<'static>>();
                    crate::dma::asynch::handle_out_interrupt::<$dma_peri<'static>>();
                }

                static INFO: ChannelInfo = ChannelInfo {
                    peripheral_interrupt: Interrupt::$peri,
                    async_handler: interrupt_handler,
                    compatible_peripherals: &[crate::dma::DmaPeripheral::$peri.0],
                };
                &INFO
            }

            pub(super) fn state(&self) -> &'static ChannelState {
                static STATE: ChannelState = ChannelState {
                    tx_waker: AtomicWaker::new(),
                    rx_waker: AtomicWaker::new(),
                    tx_async_flag: portable_atomic::AtomicBool::new(false),
                    rx_async_flag: portable_atomic::AtomicBool::new(false),
                };
                &STATE
            }
        }

        crate::dma::impl_channel_common!(I2sDma, $dma_peri);
    };
}