eqmap 0.9.3

EqMap: Technology Mapping w/ E-Graphs
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141

# THIS FILE IS AUTOMATICALLY GENERATED BY CARGO
#
# When uploading crates to the registry Cargo will automatically
# "normalize" Cargo.toml files for maximal compatibility
# with all versions of Cargo and also rewrite `path` dependencies
# to registry (e.g., crates.io) dependencies.
#
# If you are reading this file be aware that the original Cargo.toml
# will likely look very different (and much more reasonable).
# See Cargo.toml.orig for the original contents.

[package]
edition = "2024"
name = "eqmap"
version = "0.9.3"
build = false
include = [
    "Cargo.toml",
    "clippy.toml",
    "LICENSE",
    "README.md",
    "src/**/*.rs",
    "rules/*.celllang",
]
autolib = false
autobins = false
autoexamples = false
autotests = false
autobenches = false
default-run = "eqmap_fpga"
description = "EqMap: Technology Mapping w/ E-Graphs"
homepage = "https://cornell-zhang.github.io/eqmap/"
documentation = "https://cornell-zhang.github.io/eqmap/"
readme = "README.md"
keywords = [
    "data-structures",
    "eda",
    "netlist",
    "circuits",
    "hardware",
]
categories = [
    "data-structures",
    "compilers",
    "science",
]
license = "Apache-2.0"
repository = "https://github.com/cornell-zhang/eqmap"

[features]
cut_analysis = []
default = ["dyn_decomp"]
dyn_decomp = ["cut_analysis"]
egraph_fold = []
exact_cbc = [
    "egg/lp",
    "good_lp/coin_cbc",
]
exact_highs = [
    "egg/lp",
    "good_lp/highs",
]
graph_dumps = []

[lib]
name = "eqmap"
path = "src/lib.rs"

[[bin]]
name = "emit-verilog"
path = "src/bin/emit-verilog.rs"

[[bin]]
name = "eqmap_asic"
path = "src/bin/eqmap_asic.rs"

[[bin]]
name = "eqmap_fpga"
path = "src/bin/eqmap_fpga.rs"

[[bin]]
name = "nl_opt"
path = "src/bin/nl_opt.rs"

[[bin]]
name = "opt"
path = "src/bin/opt.rs"

[[bin]]
name = "optcell"
path = "src/bin/optcell.rs"

[[bin]]
name = "parse-verilog"
path = "src/bin/parse-verilog.rs"

[dependencies.bitvec]
version = "1.0.1"

[dependencies.clap]
version = "4.5.53"
features = ["derive"]

[dependencies.ctrlc]
version = "3.5.1"

[dependencies.egg]
version = "0.11.0"

[dependencies.good_lp]
version = "1.14.2"
optional = true

[dependencies.indicatif]
version = "0.18.3"

[dependencies.nl-compiler]
version = "0.1.15"

[dependencies.safety-net]
version = "0.5.5"
features = ["graph"]

[dependencies.serde]
version = "1.0.228"
features = ["derive"]

[dependencies.serde_json]
version = "1.0.145"

[dependencies.sv-parser]
version = "0.13.4"

[dependencies.thiserror]
version = "2.0.16"

[dependencies.toml]
version = "0.9.11"

[lints.clippy]
manual_range_contains = "allow"