eos_s3/spi/
dr0.rs

1#[doc = "Register `DR0` reader"]
2pub struct R(crate::R<DR0_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DR0_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DR0_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DR0_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `DR0` writer"]
17pub struct W(crate::W<DR0_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DR0_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DR0_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DR0_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `DR` reader - Data Register. When writing to this register, you must right-justify the data. Read data are automatically right-justified. Read = Receive FIFO buffer (SSI_RX_FIFO_DEPTH = 0x8) Write = Transmit FIFO buffer (SSI_TX_FIFO_DEPTH = 0x83)"]
38pub struct DR_R(crate::FieldReader<u16, u16>);
39impl DR_R {
40    #[inline(always)]
41    pub(crate) fn new(bits: u16) -> Self {
42        DR_R(crate::FieldReader::new(bits))
43    }
44}
45impl core::ops::Deref for DR_R {
46    type Target = crate::FieldReader<u16, u16>;
47    #[inline(always)]
48    fn deref(&self) -> &Self::Target {
49        &self.0
50    }
51}
52#[doc = "Field `DR` writer - Data Register. When writing to this register, you must right-justify the data. Read data are automatically right-justified. Read = Receive FIFO buffer (SSI_RX_FIFO_DEPTH = 0x8) Write = Transmit FIFO buffer (SSI_TX_FIFO_DEPTH = 0x83)"]
53pub struct DR_W<'a> {
54    w: &'a mut W,
55}
56impl<'a> DR_W<'a> {
57    #[doc = r"Writes raw bits to the field"]
58    #[inline(always)]
59    pub unsafe fn bits(self, value: u16) -> &'a mut W {
60        self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff);
61        self.w
62    }
63}
64impl R {
65    #[doc = "Bits 0:15 - Data Register. When writing to this register, you must right-justify the data. Read data are automatically right-justified. Read = Receive FIFO buffer (SSI_RX_FIFO_DEPTH = 0x8) Write = Transmit FIFO buffer (SSI_TX_FIFO_DEPTH = 0x83)"]
66    #[inline(always)]
67    pub fn dr(&self) -> DR_R {
68        DR_R::new((self.bits & 0xffff) as u16)
69    }
70}
71impl W {
72    #[doc = "Bits 0:15 - Data Register. When writing to this register, you must right-justify the data. Read data are automatically right-justified. Read = Receive FIFO buffer (SSI_RX_FIFO_DEPTH = 0x8) Write = Transmit FIFO buffer (SSI_TX_FIFO_DEPTH = 0x83)"]
73    #[inline(always)]
74    pub fn dr(&mut self) -> DR_W {
75        DR_W { w: self }
76    }
77    #[doc = "Writes raw bits to the register."]
78    #[inline(always)]
79    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
80        self.0.bits(bits);
81        self
82    }
83}
84#[doc = "The SPI Master data register is a 16-bit read/write buffer for the transmit/receive FIFOs. When the register is read, data in the receive FIFO buffer is accessed. When it is written to, data are moved into the transmit FIFO buffer; a write can occur only when SSI_EN = 1. FIFOs are reset when SSI_EN = 0. Please refer to SSIENR register (0x008) to enable and disable the SPI Master. The DR register in the SPI Master occupies 131(for TX)/8(for RX) 32-bit address locations of the memory map to facilitate AHB burst transfers. Writing to any of these address locations has the same effect as pushing the data from the pwdata bus into the transmit FIFO. Reading from any of these locations has the same effect as popping data from the receive FIFO onto the prdata bus. The FIFO buffers on the SPI Master are not addressable.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dr0](index.html) module"]
85pub struct DR0_SPEC;
86impl crate::RegisterSpec for DR0_SPEC {
87    type Ux = u32;
88}
89#[doc = "`read()` method returns [dr0::R](R) reader structure"]
90impl crate::Readable for DR0_SPEC {
91    type Reader = R;
92}
93#[doc = "`write(|w| ..)` method takes [dr0::W](W) writer structure"]
94impl crate::Writable for DR0_SPEC {
95    type Writer = W;
96}
97#[doc = "`reset()` method sets DR0 to value 0"]
98impl crate::Resettable for DR0_SPEC {
99    #[inline(always)]
100    fn reset_value() -> Self::Ux {
101        0
102    }
103}
eos_s3/spi/dr0.rs

eos_s3/spi/
dr0.rs
