eos_s3/cru/
clk_ctrl_a_1.rs

1#[doc = "Register `CLK_CTRL_A_1` reader"]
2pub struct R(crate::R<CLK_CTRL_A_1_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CLK_CTRL_A_1_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CLK_CTRL_A_1_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CLK_CTRL_A_1_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CLK_CTRL_A_1` writer"]
17pub struct W(crate::W<CLK_CTRL_A_1_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CLK_CTRL_A_1_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CLK_CTRL_A_1_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CLK_CTRL_A_1_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Select the clock source\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39#[repr(u8)]
40pub enum CLOCK_SOURCE_SELECTION_A {
41    #[doc = "0: Selects the High speed/Divided clock"]
42    WITH_HS_CLK = 0,
43    #[doc = "1: Selects the 32KHz oscillator"]
44    WITH_32KHZ_CLK = 1,
45}
46impl From<CLOCK_SOURCE_SELECTION_A> for u8 {
47    #[inline(always)]
48    fn from(variant: CLOCK_SOURCE_SELECTION_A) -> Self {
49        variant as _
50    }
51}
52#[doc = "Field `Clock_Source_Selection` reader - Select the clock source"]
53pub struct CLOCK_SOURCE_SELECTION_R(
54    crate::FieldReader<u8, CLOCK_SOURCE_SELECTION_A>,
55);
56impl CLOCK_SOURCE_SELECTION_R {
57    #[inline(always)]
58    pub(crate) fn new(bits: u8) -> Self {
59        CLOCK_SOURCE_SELECTION_R(crate::FieldReader::new(bits))
60    }
61    #[doc = r"Get enumerated values variant"]
62    #[inline(always)]
63    pub fn variant(&self) -> Option<CLOCK_SOURCE_SELECTION_A> {
64        match self.bits {
65            0 => Some(CLOCK_SOURCE_SELECTION_A::WITH_HS_CLK),
66            1 => Some(CLOCK_SOURCE_SELECTION_A::WITH_32KHZ_CLK),
67            _ => None,
68        }
69    }
70    #[doc = "Checks if the value of the field is `WITH_HS_CLK`"]
71    #[inline(always)]
72    pub fn is_with_hs_clk(&self) -> bool {
73        **self == CLOCK_SOURCE_SELECTION_A::WITH_HS_CLK
74    }
75    #[doc = "Checks if the value of the field is `WITH_32KHZ_CLK`"]
76    #[inline(always)]
77    pub fn is_with_32khz_clk(&self) -> bool {
78        **self == CLOCK_SOURCE_SELECTION_A::WITH_32KHZ_CLK
79    }
80}
81impl core::ops::Deref for CLOCK_SOURCE_SELECTION_R {
82    type Target = crate::FieldReader<u8, CLOCK_SOURCE_SELECTION_A>;
83    #[inline(always)]
84    fn deref(&self) -> &Self::Target {
85        &self.0
86    }
87}
88#[doc = "Field `Clock_Source_Selection` writer - Select the clock source"]
89pub struct CLOCK_SOURCE_SELECTION_W<'a> {
90    w: &'a mut W,
91}
92impl<'a> CLOCK_SOURCE_SELECTION_W<'a> {
93    #[doc = r"Writes `variant` to the field"]
94    #[inline(always)]
95    pub fn variant(self, variant: CLOCK_SOURCE_SELECTION_A) -> &'a mut W {
96        unsafe { self.bits(variant.into()) }
97    }
98    #[doc = "Selects the High speed/Divided clock"]
99    #[inline(always)]
100    pub fn with_hs_clk(self) -> &'a mut W {
101        self.variant(CLOCK_SOURCE_SELECTION_A::WITH_HS_CLK)
102    }
103    #[doc = "Selects the 32KHz oscillator"]
104    #[inline(always)]
105    pub fn with_32khz_clk(self) -> &'a mut W {
106        self.variant(CLOCK_SOURCE_SELECTION_A::WITH_32KHZ_CLK)
107    }
108    #[doc = r"Writes raw bits to the field"]
109    #[inline(always)]
110    pub unsafe fn bits(self, value: u8) -> &'a mut W {
111        self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03);
112        self.w
113    }
114}
115impl R {
116    #[doc = "Bits 0:1 - Select the clock source"]
117    #[inline(always)]
118    pub fn clock_source_selection(&self) -> CLOCK_SOURCE_SELECTION_R {
119        CLOCK_SOURCE_SELECTION_R::new((self.bits & 0x03) as u8)
120    }
121}
122impl W {
123    #[doc = "Bits 0:1 - Select the clock source"]
124    #[inline(always)]
125    pub fn clock_source_selection(&mut self) -> CLOCK_SOURCE_SELECTION_W {
126        CLOCK_SOURCE_SELECTION_W { w: self }
127    }
128    #[doc = "Writes raw bits to the register."]
129    #[inline(always)]
130    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
131        self.0.bits(bits);
132        self
133    }
134}
135#[doc = "For Clock 10 (SYNC Up on A0 and AHB Interface of Batching Memory, AUDIO DMA, M4 SRAMs,M4 Bus Matrix and Trace block)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk_ctrl_a_1](index.html) module"]
136pub struct CLK_CTRL_A_1_SPEC;
137impl crate::RegisterSpec for CLK_CTRL_A_1_SPEC {
138    type Ux = u32;
139}
140#[doc = "`read()` method returns [clk_ctrl_a_1::R](R) reader structure"]
141impl crate::Readable for CLK_CTRL_A_1_SPEC {
142    type Reader = R;
143}
144#[doc = "`write(|w| ..)` method takes [clk_ctrl_a_1::W](W) writer structure"]
145impl crate::Writable for CLK_CTRL_A_1_SPEC {
146    type Writer = W;
147}
148#[doc = "`reset()` method sets CLK_CTRL_A_1 to value 0"]
149impl crate::Resettable for CLK_CTRL_A_1_SPEC {
150    #[inline(always)]
151    fn reset_value() -> Self::Ux {
152        0
153    }
154}
eos_s3/cru/clk_ctrl_a_1.rs

eos_s3/cru/
clk_ctrl_a_1.rs
