eos_s3/spi/
ctrlr0.rs

1#[doc = "Register `CTRLR0` reader"]
2pub struct R(crate::R<CTRLR0_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CTRLR0_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CTRLR0_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CTRLR0_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CTRLR0` writer"]
17pub struct W(crate::W<CTRLR0_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CTRLR0_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CTRLR0_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CTRLR0_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Data Frame Size. Dependencies: When SSI_HC_FRF=1, SCPH bit is a read-only bit, with its value set by SSI_DFLT_SCPH. Selects the data frame length. When the data frame size is programmed to be less than 16 bits, the receive data are automatically right-justified by the receive logic, with the upper bits of the receive FIFO zero-padded. You must right-justify transmit data before writing into the transmit FIFO. The transmit logic ignores the upper unused bits when transmitting the data. For the field decode, refer to Table 6-2.\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39#[repr(u8)]
40pub enum DFS_A {
41    #[doc = "3: 4 bit serial data transfer"]
42    WORD_4BIT = 3,
43    #[doc = "4: 5 bit serial data transfer"]
44    WORD_5BIT = 4,
45    #[doc = "5: 6 bit serial data transfer"]
46    WORD_6BIT = 5,
47    #[doc = "6: 7 bit serial data transfer"]
48    WORD_7BIT = 6,
49    #[doc = "7: 8 bit serial data transfer"]
50    WORD_8BIT = 7,
51    #[doc = "8: 9 bit serial data transfer"]
52    WORD_9BIT = 8,
53    #[doc = "9: 10 bit serial data transfer"]
54    WORD_10BIT = 9,
55    #[doc = "10: 11 bit serial data transfer"]
56    WORD_11BIT = 10,
57    #[doc = "11: 12 bit serial data transfer"]
58    WORD_12BIT = 11,
59    #[doc = "12: 13 bit serial data transfer"]
60    WORD_13BIT = 12,
61    #[doc = "13: 14 bit serial data transfer"]
62    WORD_14BIT = 13,
63    #[doc = "14: 15 bit serial data transfer"]
64    WORD_15BIT = 14,
65    #[doc = "15: 16 bit serial data transfer"]
66    WORD_16BIT = 15,
67}
68impl From<DFS_A> for u8 {
69    #[inline(always)]
70    fn from(variant: DFS_A) -> Self {
71        variant as _
72    }
73}
74#[doc = "Field `DFS` reader - Data Frame Size. Dependencies: When SSI_HC_FRF=1, SCPH bit is a read-only bit, with its value set by SSI_DFLT_SCPH. Selects the data frame length. When the data frame size is programmed to be less than 16 bits, the receive data are automatically right-justified by the receive logic, with the upper bits of the receive FIFO zero-padded. You must right-justify transmit data before writing into the transmit FIFO. The transmit logic ignores the upper unused bits when transmitting the data. For the field decode, refer to Table 6-2."]
75pub struct DFS_R(crate::FieldReader<u8, DFS_A>);
76impl DFS_R {
77    #[inline(always)]
78    pub(crate) fn new(bits: u8) -> Self {
79        DFS_R(crate::FieldReader::new(bits))
80    }
81    #[doc = r"Get enumerated values variant"]
82    #[inline(always)]
83    pub fn variant(&self) -> Option<DFS_A> {
84        match self.bits {
85            3 => Some(DFS_A::WORD_4BIT),
86            4 => Some(DFS_A::WORD_5BIT),
87            5 => Some(DFS_A::WORD_6BIT),
88            6 => Some(DFS_A::WORD_7BIT),
89            7 => Some(DFS_A::WORD_8BIT),
90            8 => Some(DFS_A::WORD_9BIT),
91            9 => Some(DFS_A::WORD_10BIT),
92            10 => Some(DFS_A::WORD_11BIT),
93            11 => Some(DFS_A::WORD_12BIT),
94            12 => Some(DFS_A::WORD_13BIT),
95            13 => Some(DFS_A::WORD_14BIT),
96            14 => Some(DFS_A::WORD_15BIT),
97            15 => Some(DFS_A::WORD_16BIT),
98            _ => None,
99        }
100    }
101    #[doc = "Checks if the value of the field is `WORD_4BIT`"]
102    #[inline(always)]
103    pub fn is_word_4bit(&self) -> bool {
104        **self == DFS_A::WORD_4BIT
105    }
106    #[doc = "Checks if the value of the field is `WORD_5BIT`"]
107    #[inline(always)]
108    pub fn is_word_5bit(&self) -> bool {
109        **self == DFS_A::WORD_5BIT
110    }
111    #[doc = "Checks if the value of the field is `WORD_6BIT`"]
112    #[inline(always)]
113    pub fn is_word_6bit(&self) -> bool {
114        **self == DFS_A::WORD_6BIT
115    }
116    #[doc = "Checks if the value of the field is `WORD_7BIT`"]
117    #[inline(always)]
118    pub fn is_word_7bit(&self) -> bool {
119        **self == DFS_A::WORD_7BIT
120    }
121    #[doc = "Checks if the value of the field is `WORD_8BIT`"]
122    #[inline(always)]
123    pub fn is_word_8bit(&self) -> bool {
124        **self == DFS_A::WORD_8BIT
125    }
126    #[doc = "Checks if the value of the field is `WORD_9BIT`"]
127    #[inline(always)]
128    pub fn is_word_9bit(&self) -> bool {
129        **self == DFS_A::WORD_9BIT
130    }
131    #[doc = "Checks if the value of the field is `WORD_10BIT`"]
132    #[inline(always)]
133    pub fn is_word_10bit(&self) -> bool {
134        **self == DFS_A::WORD_10BIT
135    }
136    #[doc = "Checks if the value of the field is `WORD_11BIT`"]
137    #[inline(always)]
138    pub fn is_word_11bit(&self) -> bool {
139        **self == DFS_A::WORD_11BIT
140    }
141    #[doc = "Checks if the value of the field is `WORD_12BIT`"]
142    #[inline(always)]
143    pub fn is_word_12bit(&self) -> bool {
144        **self == DFS_A::WORD_12BIT
145    }
146    #[doc = "Checks if the value of the field is `WORD_13BIT`"]
147    #[inline(always)]
148    pub fn is_word_13bit(&self) -> bool {
149        **self == DFS_A::WORD_13BIT
150    }
151    #[doc = "Checks if the value of the field is `WORD_14BIT`"]
152    #[inline(always)]
153    pub fn is_word_14bit(&self) -> bool {
154        **self == DFS_A::WORD_14BIT
155    }
156    #[doc = "Checks if the value of the field is `WORD_15BIT`"]
157    #[inline(always)]
158    pub fn is_word_15bit(&self) -> bool {
159        **self == DFS_A::WORD_15BIT
160    }
161    #[doc = "Checks if the value of the field is `WORD_16BIT`"]
162    #[inline(always)]
163    pub fn is_word_16bit(&self) -> bool {
164        **self == DFS_A::WORD_16BIT
165    }
166}
167impl core::ops::Deref for DFS_R {
168    type Target = crate::FieldReader<u8, DFS_A>;
169    #[inline(always)]
170    fn deref(&self) -> &Self::Target {
171        &self.0
172    }
173}
174#[doc = "Field `DFS` writer - Data Frame Size. Dependencies: When SSI_HC_FRF=1, SCPH bit is a read-only bit, with its value set by SSI_DFLT_SCPH. Selects the data frame length. When the data frame size is programmed to be less than 16 bits, the receive data are automatically right-justified by the receive logic, with the upper bits of the receive FIFO zero-padded. You must right-justify transmit data before writing into the transmit FIFO. The transmit logic ignores the upper unused bits when transmitting the data. For the field decode, refer to Table 6-2."]
175pub struct DFS_W<'a> {
176    w: &'a mut W,
177}
178impl<'a> DFS_W<'a> {
179    #[doc = r"Writes `variant` to the field"]
180    #[inline(always)]
181    pub fn variant(self, variant: DFS_A) -> &'a mut W {
182        unsafe { self.bits(variant.into()) }
183    }
184    #[doc = "4 bit serial data transfer"]
185    #[inline(always)]
186    pub fn word_4bit(self) -> &'a mut W {
187        self.variant(DFS_A::WORD_4BIT)
188    }
189    #[doc = "5 bit serial data transfer"]
190    #[inline(always)]
191    pub fn word_5bit(self) -> &'a mut W {
192        self.variant(DFS_A::WORD_5BIT)
193    }
194    #[doc = "6 bit serial data transfer"]
195    #[inline(always)]
196    pub fn word_6bit(self) -> &'a mut W {
197        self.variant(DFS_A::WORD_6BIT)
198    }
199    #[doc = "7 bit serial data transfer"]
200    #[inline(always)]
201    pub fn word_7bit(self) -> &'a mut W {
202        self.variant(DFS_A::WORD_7BIT)
203    }
204    #[doc = "8 bit serial data transfer"]
205    #[inline(always)]
206    pub fn word_8bit(self) -> &'a mut W {
207        self.variant(DFS_A::WORD_8BIT)
208    }
209    #[doc = "9 bit serial data transfer"]
210    #[inline(always)]
211    pub fn word_9bit(self) -> &'a mut W {
212        self.variant(DFS_A::WORD_9BIT)
213    }
214    #[doc = "10 bit serial data transfer"]
215    #[inline(always)]
216    pub fn word_10bit(self) -> &'a mut W {
217        self.variant(DFS_A::WORD_10BIT)
218    }
219    #[doc = "11 bit serial data transfer"]
220    #[inline(always)]
221    pub fn word_11bit(self) -> &'a mut W {
222        self.variant(DFS_A::WORD_11BIT)
223    }
224    #[doc = "12 bit serial data transfer"]
225    #[inline(always)]
226    pub fn word_12bit(self) -> &'a mut W {
227        self.variant(DFS_A::WORD_12BIT)
228    }
229    #[doc = "13 bit serial data transfer"]
230    #[inline(always)]
231    pub fn word_13bit(self) -> &'a mut W {
232        self.variant(DFS_A::WORD_13BIT)
233    }
234    #[doc = "14 bit serial data transfer"]
235    #[inline(always)]
236    pub fn word_14bit(self) -> &'a mut W {
237        self.variant(DFS_A::WORD_14BIT)
238    }
239    #[doc = "15 bit serial data transfer"]
240    #[inline(always)]
241    pub fn word_15bit(self) -> &'a mut W {
242        self.variant(DFS_A::WORD_15BIT)
243    }
244    #[doc = "16 bit serial data transfer"]
245    #[inline(always)]
246    pub fn word_16bit(self) -> &'a mut W {
247        self.variant(DFS_A::WORD_16BIT)
248    }
249    #[doc = r"Writes raw bits to the field"]
250    #[inline(always)]
251    pub unsafe fn bits(self, value: u8) -> &'a mut W {
252        self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f);
253        self.w
254    }
255}
256#[doc = "Field `FRF` reader - 00 - Motorola SPI only"]
257pub struct FRF_R(crate::FieldReader<u8, u8>);
258impl FRF_R {
259    #[inline(always)]
260    pub(crate) fn new(bits: u8) -> Self {
261        FRF_R(crate::FieldReader::new(bits))
262    }
263}
264impl core::ops::Deref for FRF_R {
265    type Target = crate::FieldReader<u8, u8>;
266    #[inline(always)]
267    fn deref(&self) -> &Self::Target {
268        &self.0
269    }
270}
271#[doc = "Field `FRF` writer - 00 - Motorola SPI only"]
272pub struct FRF_W<'a> {
273    w: &'a mut W,
274}
275impl<'a> FRF_W<'a> {
276    #[doc = r"Writes raw bits to the field"]
277    #[inline(always)]
278    pub unsafe fn bits(self, value: u8) -> &'a mut W {
279        self.w.bits =
280            (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4);
281        self.w
282    }
283}
284#[doc = "Serial Clock Phase. Valid when the frame format (FRF) is set to Motorola SPI. The serial clock phase selects the relationship of the serial clock with the slave select signal. When SCPH = 0, data are captured on the first edge of the serial clock. When SCPH = 1, the serial clock starts toggling one cycle after the slave select line is activated, and data are captured on the second edge of the serial clock. Dependencies: When SSI_HC_FRF=1, SCPH bit is a read-only bit, with its value set by SSI_DFLT_SCPH.\n\nValue on reset: 0"]
285#[derive(Clone, Copy, Debug, PartialEq)]
286pub enum SCPH_A {
287    #[doc = "0: Serial clock toggles in middle of first data bit"]
288    TOGGLE_MIDDLE = 0,
289    #[doc = "1: Serial clock toggles at start of first data bit"]
290    TOGGLE_START = 1,
291}
292impl From<SCPH_A> for bool {
293    #[inline(always)]
294    fn from(variant: SCPH_A) -> Self {
295        variant as u8 != 0
296    }
297}
298#[doc = "Field `SCPH` reader - Serial Clock Phase. Valid when the frame format (FRF) is set to Motorola SPI. The serial clock phase selects the relationship of the serial clock with the slave select signal. When SCPH = 0, data are captured on the first edge of the serial clock. When SCPH = 1, the serial clock starts toggling one cycle after the slave select line is activated, and data are captured on the second edge of the serial clock. Dependencies: When SSI_HC_FRF=1, SCPH bit is a read-only bit, with its value set by SSI_DFLT_SCPH."]
299pub struct SCPH_R(crate::FieldReader<bool, SCPH_A>);
300impl SCPH_R {
301    #[inline(always)]
302    pub(crate) fn new(bits: bool) -> Self {
303        SCPH_R(crate::FieldReader::new(bits))
304    }
305    #[doc = r"Get enumerated values variant"]
306    #[inline(always)]
307    pub fn variant(&self) -> SCPH_A {
308        match self.bits {
309            false => SCPH_A::TOGGLE_MIDDLE,
310            true => SCPH_A::TOGGLE_START,
311        }
312    }
313    #[doc = "Checks if the value of the field is `TOGGLE_MIDDLE`"]
314    #[inline(always)]
315    pub fn is_toggle_middle(&self) -> bool {
316        **self == SCPH_A::TOGGLE_MIDDLE
317    }
318    #[doc = "Checks if the value of the field is `TOGGLE_START`"]
319    #[inline(always)]
320    pub fn is_toggle_start(&self) -> bool {
321        **self == SCPH_A::TOGGLE_START
322    }
323}
324impl core::ops::Deref for SCPH_R {
325    type Target = crate::FieldReader<bool, SCPH_A>;
326    #[inline(always)]
327    fn deref(&self) -> &Self::Target {
328        &self.0
329    }
330}
331#[doc = "Field `SCPH` writer - Serial Clock Phase. Valid when the frame format (FRF) is set to Motorola SPI. The serial clock phase selects the relationship of the serial clock with the slave select signal. When SCPH = 0, data are captured on the first edge of the serial clock. When SCPH = 1, the serial clock starts toggling one cycle after the slave select line is activated, and data are captured on the second edge of the serial clock. Dependencies: When SSI_HC_FRF=1, SCPH bit is a read-only bit, with its value set by SSI_DFLT_SCPH."]
332pub struct SCPH_W<'a> {
333    w: &'a mut W,
334}
335impl<'a> SCPH_W<'a> {
336    #[doc = r"Writes `variant` to the field"]
337    #[inline(always)]
338    pub fn variant(self, variant: SCPH_A) -> &'a mut W {
339        self.bit(variant.into())
340    }
341    #[doc = "Serial clock toggles in middle of first data bit"]
342    #[inline(always)]
343    pub fn toggle_middle(self) -> &'a mut W {
344        self.variant(SCPH_A::TOGGLE_MIDDLE)
345    }
346    #[doc = "Serial clock toggles at start of first data bit"]
347    #[inline(always)]
348    pub fn toggle_start(self) -> &'a mut W {
349        self.variant(SCPH_A::TOGGLE_START)
350    }
351    #[doc = r"Sets the field bit"]
352    #[inline(always)]
353    pub fn set_bit(self) -> &'a mut W {
354        self.bit(true)
355    }
356    #[doc = r"Clears the field bit"]
357    #[inline(always)]
358    pub fn clear_bit(self) -> &'a mut W {
359        self.bit(false)
360    }
361    #[doc = r"Writes raw bits to the field"]
362    #[inline(always)]
363    pub fn bit(self, value: bool) -> &'a mut W {
364        self.w.bits =
365            (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
366        self.w
367    }
368}
369#[doc = "Serial Clock Polarity. Valid when the frame format (FRF) is set to Motorola SPI. Used to select the polarity of the inactive serial clock, which is held inactive when the SPI Master is not actively transferring data on the serial bus. Dependencies: When SSI_HC_FRF=1, SCPOL bit is a read-only bit with its value set by SSI_DFLT_SCPOL.\n\nValue on reset: 0"]
370#[derive(Clone, Copy, Debug, PartialEq)]
371pub enum SCPOL_A {
372    #[doc = "0: Inactive state of serial clock is low"]
373    INACTIVE_LOW = 0,
374    #[doc = "1: Inactive state of serial clock is high"]
375    INACTIVE_HIGH = 1,
376}
377impl From<SCPOL_A> for bool {
378    #[inline(always)]
379    fn from(variant: SCPOL_A) -> Self {
380        variant as u8 != 0
381    }
382}
383#[doc = "Field `SCPOL` reader - Serial Clock Polarity. Valid when the frame format (FRF) is set to Motorola SPI. Used to select the polarity of the inactive serial clock, which is held inactive when the SPI Master is not actively transferring data on the serial bus. Dependencies: When SSI_HC_FRF=1, SCPOL bit is a read-only bit with its value set by SSI_DFLT_SCPOL."]
384pub struct SCPOL_R(crate::FieldReader<bool, SCPOL_A>);
385impl SCPOL_R {
386    #[inline(always)]
387    pub(crate) fn new(bits: bool) -> Self {
388        SCPOL_R(crate::FieldReader::new(bits))
389    }
390    #[doc = r"Get enumerated values variant"]
391    #[inline(always)]
392    pub fn variant(&self) -> SCPOL_A {
393        match self.bits {
394            false => SCPOL_A::INACTIVE_LOW,
395            true => SCPOL_A::INACTIVE_HIGH,
396        }
397    }
398    #[doc = "Checks if the value of the field is `INACTIVE_LOW`"]
399    #[inline(always)]
400    pub fn is_inactive_low(&self) -> bool {
401        **self == SCPOL_A::INACTIVE_LOW
402    }
403    #[doc = "Checks if the value of the field is `INACTIVE_HIGH`"]
404    #[inline(always)]
405    pub fn is_inactive_high(&self) -> bool {
406        **self == SCPOL_A::INACTIVE_HIGH
407    }
408}
409impl core::ops::Deref for SCPOL_R {
410    type Target = crate::FieldReader<bool, SCPOL_A>;
411    #[inline(always)]
412    fn deref(&self) -> &Self::Target {
413        &self.0
414    }
415}
416#[doc = "Field `SCPOL` writer - Serial Clock Polarity. Valid when the frame format (FRF) is set to Motorola SPI. Used to select the polarity of the inactive serial clock, which is held inactive when the SPI Master is not actively transferring data on the serial bus. Dependencies: When SSI_HC_FRF=1, SCPOL bit is a read-only bit with its value set by SSI_DFLT_SCPOL."]
417pub struct SCPOL_W<'a> {
418    w: &'a mut W,
419}
420impl<'a> SCPOL_W<'a> {
421    #[doc = r"Writes `variant` to the field"]
422    #[inline(always)]
423    pub fn variant(self, variant: SCPOL_A) -> &'a mut W {
424        self.bit(variant.into())
425    }
426    #[doc = "Inactive state of serial clock is low"]
427    #[inline(always)]
428    pub fn inactive_low(self) -> &'a mut W {
429        self.variant(SCPOL_A::INACTIVE_LOW)
430    }
431    #[doc = "Inactive state of serial clock is high"]
432    #[inline(always)]
433    pub fn inactive_high(self) -> &'a mut W {
434        self.variant(SCPOL_A::INACTIVE_HIGH)
435    }
436    #[doc = r"Sets the field bit"]
437    #[inline(always)]
438    pub fn set_bit(self) -> &'a mut W {
439        self.bit(true)
440    }
441    #[doc = r"Clears the field bit"]
442    #[inline(always)]
443    pub fn clear_bit(self) -> &'a mut W {
444        self.bit(false)
445    }
446    #[doc = r"Writes raw bits to the field"]
447    #[inline(always)]
448    pub fn bit(self, value: bool) -> &'a mut W {
449        self.w.bits =
450            (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7);
451        self.w
452    }
453}
454#[doc = "Transfer Mode. Selects the mode of transfer for serial communication. This field does not affect the transfer duplicity. Only indicates whether the receive or transmit data are valid. In transmit-only mode, data received from the external device is not valid and is not stored in the receive FIFO memory; it is overwritten on the next transfer. In receive-only mode, transmitted data are not valid. After the first write to the transmit FIFO, the same word is retransmitted for the duration of the transfer. In transmit-and-receive mode, both transmit and receive data are valid. The transfer continues until the transmit FIFO is empty. Data received from the external device are stored into the receive FIFO memory, where it can be accessed by the host processor. In eeprom-read mode, receive data is not valid while control data is being transmitted. When all control data is sent to the EEPROM, receive data becomes valid and transmit data becomes invalid. All data in the transmit FIFO is considered control data in this mode. This transfer mode is only valid when the SPI Master is configured as a master device.\n\nValue on reset: 0"]
455#[derive(Clone, Copy, Debug, PartialEq)]
456#[repr(u8)]
457pub enum TMOD_A {
458    #[doc = "0: Transmit and receive"]
459    TX_RX = 0,
460    #[doc = "1: Transmit only"]
461    TX = 1,
462    #[doc = "2: Receive only"]
463    RX = 2,
464    #[doc = "3: EEPROM read"]
465    EEPROM = 3,
466}
467impl From<TMOD_A> for u8 {
468    #[inline(always)]
469    fn from(variant: TMOD_A) -> Self {
470        variant as _
471    }
472}
473#[doc = "Field `TMOD` reader - Transfer Mode. Selects the mode of transfer for serial communication. This field does not affect the transfer duplicity. Only indicates whether the receive or transmit data are valid. In transmit-only mode, data received from the external device is not valid and is not stored in the receive FIFO memory; it is overwritten on the next transfer. In receive-only mode, transmitted data are not valid. After the first write to the transmit FIFO, the same word is retransmitted for the duration of the transfer. In transmit-and-receive mode, both transmit and receive data are valid. The transfer continues until the transmit FIFO is empty. Data received from the external device are stored into the receive FIFO memory, where it can be accessed by the host processor. In eeprom-read mode, receive data is not valid while control data is being transmitted. When all control data is sent to the EEPROM, receive data becomes valid and transmit data becomes invalid. All data in the transmit FIFO is considered control data in this mode. This transfer mode is only valid when the SPI Master is configured as a master device."]
474pub struct TMOD_R(crate::FieldReader<u8, TMOD_A>);
475impl TMOD_R {
476    #[inline(always)]
477    pub(crate) fn new(bits: u8) -> Self {
478        TMOD_R(crate::FieldReader::new(bits))
479    }
480    #[doc = r"Get enumerated values variant"]
481    #[inline(always)]
482    pub fn variant(&self) -> TMOD_A {
483        match self.bits {
484            0 => TMOD_A::TX_RX,
485            1 => TMOD_A::TX,
486            2 => TMOD_A::RX,
487            3 => TMOD_A::EEPROM,
488            _ => unreachable!(),
489        }
490    }
491    #[doc = "Checks if the value of the field is `TX_RX`"]
492    #[inline(always)]
493    pub fn is_tx_rx(&self) -> bool {
494        **self == TMOD_A::TX_RX
495    }
496    #[doc = "Checks if the value of the field is `TX`"]
497    #[inline(always)]
498    pub fn is_tx(&self) -> bool {
499        **self == TMOD_A::TX
500    }
501    #[doc = "Checks if the value of the field is `RX`"]
502    #[inline(always)]
503    pub fn is_rx(&self) -> bool {
504        **self == TMOD_A::RX
505    }
506    #[doc = "Checks if the value of the field is `EEPROM`"]
507    #[inline(always)]
508    pub fn is_eeprom(&self) -> bool {
509        **self == TMOD_A::EEPROM
510    }
511}
512impl core::ops::Deref for TMOD_R {
513    type Target = crate::FieldReader<u8, TMOD_A>;
514    #[inline(always)]
515    fn deref(&self) -> &Self::Target {
516        &self.0
517    }
518}
519#[doc = "Field `TMOD` writer - Transfer Mode. Selects the mode of transfer for serial communication. This field does not affect the transfer duplicity. Only indicates whether the receive or transmit data are valid. In transmit-only mode, data received from the external device is not valid and is not stored in the receive FIFO memory; it is overwritten on the next transfer. In receive-only mode, transmitted data are not valid. After the first write to the transmit FIFO, the same word is retransmitted for the duration of the transfer. In transmit-and-receive mode, both transmit and receive data are valid. The transfer continues until the transmit FIFO is empty. Data received from the external device are stored into the receive FIFO memory, where it can be accessed by the host processor. In eeprom-read mode, receive data is not valid while control data is being transmitted. When all control data is sent to the EEPROM, receive data becomes valid and transmit data becomes invalid. All data in the transmit FIFO is considered control data in this mode. This transfer mode is only valid when the SPI Master is configured as a master device."]
520pub struct TMOD_W<'a> {
521    w: &'a mut W,
522}
523impl<'a> TMOD_W<'a> {
524    #[doc = r"Writes `variant` to the field"]
525    #[inline(always)]
526    pub fn variant(self, variant: TMOD_A) -> &'a mut W {
527        self.bits(variant.into())
528    }
529    #[doc = "Transmit and receive"]
530    #[inline(always)]
531    pub fn tx_rx(self) -> &'a mut W {
532        self.variant(TMOD_A::TX_RX)
533    }
534    #[doc = "Transmit only"]
535    #[inline(always)]
536    pub fn tx(self) -> &'a mut W {
537        self.variant(TMOD_A::TX)
538    }
539    #[doc = "Receive only"]
540    #[inline(always)]
541    pub fn rx(self) -> &'a mut W {
542        self.variant(TMOD_A::RX)
543    }
544    #[doc = "EEPROM read"]
545    #[inline(always)]
546    pub fn eeprom(self) -> &'a mut W {
547        self.variant(TMOD_A::EEPROM)
548    }
549    #[doc = r"Writes raw bits to the field"]
550    #[inline(always)]
551    pub fn bits(self, value: u8) -> &'a mut W {
552        self.w.bits =
553            (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8);
554        self.w
555    }
556}
557#[doc = "Field `SLV_OE` reader - No function for SPI Master. Slave usage only."]
558pub struct SLV_OE_R(crate::FieldReader<bool, bool>);
559impl SLV_OE_R {
560    #[inline(always)]
561    pub(crate) fn new(bits: bool) -> Self {
562        SLV_OE_R(crate::FieldReader::new(bits))
563    }
564}
565impl core::ops::Deref for SLV_OE_R {
566    type Target = crate::FieldReader<bool, bool>;
567    #[inline(always)]
568    fn deref(&self) -> &Self::Target {
569        &self.0
570    }
571}
572#[doc = "Field `SLV_OE` writer - No function for SPI Master. Slave usage only."]
573pub struct SLV_OE_W<'a> {
574    w: &'a mut W,
575}
576impl<'a> SLV_OE_W<'a> {
577    #[doc = r"Sets the field bit"]
578    #[inline(always)]
579    pub fn set_bit(self) -> &'a mut W {
580        self.bit(true)
581    }
582    #[doc = r"Clears the field bit"]
583    #[inline(always)]
584    pub fn clear_bit(self) -> &'a mut W {
585        self.bit(false)
586    }
587    #[doc = r"Writes raw bits to the field"]
588    #[inline(always)]
589    pub fn bit(self, value: bool) -> &'a mut W {
590        self.w.bits =
591            (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10);
592        self.w
593    }
594}
595#[doc = "Shift Register Loop. Used for testing purposes only. When internally active, connects the transmit shift register output to the receive shift register input. Can be used in both serial slave and serial-master modes. When the SPI Master is configured as a slave in loopback mode, the ss_in_n and ssi_clk signals must be provided by an external source. In this mode, the slave cannot generate these signals because there is nothing to which to loop back.\n\nValue on reset: 0"]
596#[derive(Clone, Copy, Debug, PartialEq)]
597pub enum SRL_A {
598    #[doc = "0: Normal mode operation"]
599    NORMAL = 0,
600    #[doc = "1: test mode operation"]
601    TEST = 1,
602}
603impl From<SRL_A> for bool {
604    #[inline(always)]
605    fn from(variant: SRL_A) -> Self {
606        variant as u8 != 0
607    }
608}
609#[doc = "Field `SRL` reader - Shift Register Loop. Used for testing purposes only. When internally active, connects the transmit shift register output to the receive shift register input. Can be used in both serial slave and serial-master modes. When the SPI Master is configured as a slave in loopback mode, the ss_in_n and ssi_clk signals must be provided by an external source. In this mode, the slave cannot generate these signals because there is nothing to which to loop back."]
610pub struct SRL_R(crate::FieldReader<bool, SRL_A>);
611impl SRL_R {
612    #[inline(always)]
613    pub(crate) fn new(bits: bool) -> Self {
614        SRL_R(crate::FieldReader::new(bits))
615    }
616    #[doc = r"Get enumerated values variant"]
617    #[inline(always)]
618    pub fn variant(&self) -> SRL_A {
619        match self.bits {
620            false => SRL_A::NORMAL,
621            true => SRL_A::TEST,
622        }
623    }
624    #[doc = "Checks if the value of the field is `NORMAL`"]
625    #[inline(always)]
626    pub fn is_normal(&self) -> bool {
627        **self == SRL_A::NORMAL
628    }
629    #[doc = "Checks if the value of the field is `TEST`"]
630    #[inline(always)]
631    pub fn is_test(&self) -> bool {
632        **self == SRL_A::TEST
633    }
634}
635impl core::ops::Deref for SRL_R {
636    type Target = crate::FieldReader<bool, SRL_A>;
637    #[inline(always)]
638    fn deref(&self) -> &Self::Target {
639        &self.0
640    }
641}
642#[doc = "Field `SRL` writer - Shift Register Loop. Used for testing purposes only. When internally active, connects the transmit shift register output to the receive shift register input. Can be used in both serial slave and serial-master modes. When the SPI Master is configured as a slave in loopback mode, the ss_in_n and ssi_clk signals must be provided by an external source. In this mode, the slave cannot generate these signals because there is nothing to which to loop back."]
643pub struct SRL_W<'a> {
644    w: &'a mut W,
645}
646impl<'a> SRL_W<'a> {
647    #[doc = r"Writes `variant` to the field"]
648    #[inline(always)]
649    pub fn variant(self, variant: SRL_A) -> &'a mut W {
650        self.bit(variant.into())
651    }
652    #[doc = "Normal mode operation"]
653    #[inline(always)]
654    pub fn normal(self) -> &'a mut W {
655        self.variant(SRL_A::NORMAL)
656    }
657    #[doc = "test mode operation"]
658    #[inline(always)]
659    pub fn test(self) -> &'a mut W {
660        self.variant(SRL_A::TEST)
661    }
662    #[doc = r"Sets the field bit"]
663    #[inline(always)]
664    pub fn set_bit(self) -> &'a mut W {
665        self.bit(true)
666    }
667    #[doc = r"Clears the field bit"]
668    #[inline(always)]
669    pub fn clear_bit(self) -> &'a mut W {
670        self.bit(false)
671    }
672    #[doc = r"Writes raw bits to the field"]
673    #[inline(always)]
674    pub fn bit(self, value: bool) -> &'a mut W {
675        self.w.bits =
676            (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11);
677        self.w
678    }
679}
680#[doc = "Control Frame Size. Selects the length of the control word for the Microwire frame format. For the field decode, refer to Table 6-3 on page 101\n\nValue on reset: 0"]
681#[derive(Clone, Copy, Debug, PartialEq)]
682#[repr(u8)]
683pub enum CFS_A {
684    #[doc = "0: 1 bit control word"]
685    WORD_1BIT = 0,
686    #[doc = "1: 2 bit control word"]
687    WORD_2BIT = 1,
688    #[doc = "2: 3 bit control word"]
689    WORD_3BIT = 2,
690    #[doc = "3: 4 bit control word"]
691    WORD_4BIT = 3,
692    #[doc = "4: 5 bit control word"]
693    WORD_5BIT = 4,
694    #[doc = "5: 6 bit control word"]
695    WORD_6BIT = 5,
696    #[doc = "6: 7 bit control word"]
697    WORD_7BIT = 6,
698    #[doc = "7: 8 bit control word"]
699    WORD_8BIT = 7,
700    #[doc = "8: 9 bit control word"]
701    WORD_9BIT = 8,
702    #[doc = "9: 10 bit control word"]
703    WORD_10BIT = 9,
704    #[doc = "10: 11 bit control word"]
705    WORD_11BIT = 10,
706    #[doc = "11: 12 bit control word"]
707    WORD_12BIT = 11,
708    #[doc = "12: 13 bit control word"]
709    WORD_13BIT = 12,
710    #[doc = "13: 14 bit control word"]
711    WORD_14BIT = 13,
712    #[doc = "14: 15 bit control word"]
713    WORD_15BIT = 14,
714    #[doc = "15: 16 bit control word"]
715    WORD_16BIT = 15,
716}
717impl From<CFS_A> for u8 {
718    #[inline(always)]
719    fn from(variant: CFS_A) -> Self {
720        variant as _
721    }
722}
723#[doc = "Field `CFS` reader - Control Frame Size. Selects the length of the control word for the Microwire frame format. For the field decode, refer to Table 6-3 on page 101"]
724pub struct CFS_R(crate::FieldReader<u8, CFS_A>);
725impl CFS_R {
726    #[inline(always)]
727    pub(crate) fn new(bits: u8) -> Self {
728        CFS_R(crate::FieldReader::new(bits))
729    }
730    #[doc = r"Get enumerated values variant"]
731    #[inline(always)]
732    pub fn variant(&self) -> CFS_A {
733        match self.bits {
734            0 => CFS_A::WORD_1BIT,
735            1 => CFS_A::WORD_2BIT,
736            2 => CFS_A::WORD_3BIT,
737            3 => CFS_A::WORD_4BIT,
738            4 => CFS_A::WORD_5BIT,
739            5 => CFS_A::WORD_6BIT,
740            6 => CFS_A::WORD_7BIT,
741            7 => CFS_A::WORD_8BIT,
742            8 => CFS_A::WORD_9BIT,
743            9 => CFS_A::WORD_10BIT,
744            10 => CFS_A::WORD_11BIT,
745            11 => CFS_A::WORD_12BIT,
746            12 => CFS_A::WORD_13BIT,
747            13 => CFS_A::WORD_14BIT,
748            14 => CFS_A::WORD_15BIT,
749            15 => CFS_A::WORD_16BIT,
750            _ => unreachable!(),
751        }
752    }
753    #[doc = "Checks if the value of the field is `WORD_1BIT`"]
754    #[inline(always)]
755    pub fn is_word_1bit(&self) -> bool {
756        **self == CFS_A::WORD_1BIT
757    }
758    #[doc = "Checks if the value of the field is `WORD_2BIT`"]
759    #[inline(always)]
760    pub fn is_word_2bit(&self) -> bool {
761        **self == CFS_A::WORD_2BIT
762    }
763    #[doc = "Checks if the value of the field is `WORD_3BIT`"]
764    #[inline(always)]
765    pub fn is_word_3bit(&self) -> bool {
766        **self == CFS_A::WORD_3BIT
767    }
768    #[doc = "Checks if the value of the field is `WORD_4BIT`"]
769    #[inline(always)]
770    pub fn is_word_4bit(&self) -> bool {
771        **self == CFS_A::WORD_4BIT
772    }
773    #[doc = "Checks if the value of the field is `WORD_5BIT`"]
774    #[inline(always)]
775    pub fn is_word_5bit(&self) -> bool {
776        **self == CFS_A::WORD_5BIT
777    }
778    #[doc = "Checks if the value of the field is `WORD_6BIT`"]
779    #[inline(always)]
780    pub fn is_word_6bit(&self) -> bool {
781        **self == CFS_A::WORD_6BIT
782    }
783    #[doc = "Checks if the value of the field is `WORD_7BIT`"]
784    #[inline(always)]
785    pub fn is_word_7bit(&self) -> bool {
786        **self == CFS_A::WORD_7BIT
787    }
788    #[doc = "Checks if the value of the field is `WORD_8BIT`"]
789    #[inline(always)]
790    pub fn is_word_8bit(&self) -> bool {
791        **self == CFS_A::WORD_8BIT
792    }
793    #[doc = "Checks if the value of the field is `WORD_9BIT`"]
794    #[inline(always)]
795    pub fn is_word_9bit(&self) -> bool {
796        **self == CFS_A::WORD_9BIT
797    }
798    #[doc = "Checks if the value of the field is `WORD_10BIT`"]
799    #[inline(always)]
800    pub fn is_word_10bit(&self) -> bool {
801        **self == CFS_A::WORD_10BIT
802    }
803    #[doc = "Checks if the value of the field is `WORD_11BIT`"]
804    #[inline(always)]
805    pub fn is_word_11bit(&self) -> bool {
806        **self == CFS_A::WORD_11BIT
807    }
808    #[doc = "Checks if the value of the field is `WORD_12BIT`"]
809    #[inline(always)]
810    pub fn is_word_12bit(&self) -> bool {
811        **self == CFS_A::WORD_12BIT
812    }
813    #[doc = "Checks if the value of the field is `WORD_13BIT`"]
814    #[inline(always)]
815    pub fn is_word_13bit(&self) -> bool {
816        **self == CFS_A::WORD_13BIT
817    }
818    #[doc = "Checks if the value of the field is `WORD_14BIT`"]
819    #[inline(always)]
820    pub fn is_word_14bit(&self) -> bool {
821        **self == CFS_A::WORD_14BIT
822    }
823    #[doc = "Checks if the value of the field is `WORD_15BIT`"]
824    #[inline(always)]
825    pub fn is_word_15bit(&self) -> bool {
826        **self == CFS_A::WORD_15BIT
827    }
828    #[doc = "Checks if the value of the field is `WORD_16BIT`"]
829    #[inline(always)]
830    pub fn is_word_16bit(&self) -> bool {
831        **self == CFS_A::WORD_16BIT
832    }
833}
834impl core::ops::Deref for CFS_R {
835    type Target = crate::FieldReader<u8, CFS_A>;
836    #[inline(always)]
837    fn deref(&self) -> &Self::Target {
838        &self.0
839    }
840}
841#[doc = "Field `CFS` writer - Control Frame Size. Selects the length of the control word for the Microwire frame format. For the field decode, refer to Table 6-3 on page 101"]
842pub struct CFS_W<'a> {
843    w: &'a mut W,
844}
845impl<'a> CFS_W<'a> {
846    #[doc = r"Writes `variant` to the field"]
847    #[inline(always)]
848    pub fn variant(self, variant: CFS_A) -> &'a mut W {
849        self.bits(variant.into())
850    }
851    #[doc = "1 bit control word"]
852    #[inline(always)]
853    pub fn word_1bit(self) -> &'a mut W {
854        self.variant(CFS_A::WORD_1BIT)
855    }
856    #[doc = "2 bit control word"]
857    #[inline(always)]
858    pub fn word_2bit(self) -> &'a mut W {
859        self.variant(CFS_A::WORD_2BIT)
860    }
861    #[doc = "3 bit control word"]
862    #[inline(always)]
863    pub fn word_3bit(self) -> &'a mut W {
864        self.variant(CFS_A::WORD_3BIT)
865    }
866    #[doc = "4 bit control word"]
867    #[inline(always)]
868    pub fn word_4bit(self) -> &'a mut W {
869        self.variant(CFS_A::WORD_4BIT)
870    }
871    #[doc = "5 bit control word"]
872    #[inline(always)]
873    pub fn word_5bit(self) -> &'a mut W {
874        self.variant(CFS_A::WORD_5BIT)
875    }
876    #[doc = "6 bit control word"]
877    #[inline(always)]
878    pub fn word_6bit(self) -> &'a mut W {
879        self.variant(CFS_A::WORD_6BIT)
880    }
881    #[doc = "7 bit control word"]
882    #[inline(always)]
883    pub fn word_7bit(self) -> &'a mut W {
884        self.variant(CFS_A::WORD_7BIT)
885    }
886    #[doc = "8 bit control word"]
887    #[inline(always)]
888    pub fn word_8bit(self) -> &'a mut W {
889        self.variant(CFS_A::WORD_8BIT)
890    }
891    #[doc = "9 bit control word"]
892    #[inline(always)]
893    pub fn word_9bit(self) -> &'a mut W {
894        self.variant(CFS_A::WORD_9BIT)
895    }
896    #[doc = "10 bit control word"]
897    #[inline(always)]
898    pub fn word_10bit(self) -> &'a mut W {
899        self.variant(CFS_A::WORD_10BIT)
900    }
901    #[doc = "11 bit control word"]
902    #[inline(always)]
903    pub fn word_11bit(self) -> &'a mut W {
904        self.variant(CFS_A::WORD_11BIT)
905    }
906    #[doc = "12 bit control word"]
907    #[inline(always)]
908    pub fn word_12bit(self) -> &'a mut W {
909        self.variant(CFS_A::WORD_12BIT)
910    }
911    #[doc = "13 bit control word"]
912    #[inline(always)]
913    pub fn word_13bit(self) -> &'a mut W {
914        self.variant(CFS_A::WORD_13BIT)
915    }
916    #[doc = "14 bit control word"]
917    #[inline(always)]
918    pub fn word_14bit(self) -> &'a mut W {
919        self.variant(CFS_A::WORD_14BIT)
920    }
921    #[doc = "15 bit control word"]
922    #[inline(always)]
923    pub fn word_15bit(self) -> &'a mut W {
924        self.variant(CFS_A::WORD_15BIT)
925    }
926    #[doc = "16 bit control word"]
927    #[inline(always)]
928    pub fn word_16bit(self) -> &'a mut W {
929        self.variant(CFS_A::WORD_16BIT)
930    }
931    #[doc = r"Writes raw bits to the field"]
932    #[inline(always)]
933    pub fn bits(self, value: u8) -> &'a mut W {
934        self.w.bits =
935            (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12);
936        self.w
937    }
938}
939#[doc = "Data Frame Size in 32-bit mode. Used to select the data frame size in 32-bit mode. These bits are only valid when SSI_MAX_XFER_SIZE is configured to 32. When the data frame size is programmed to be less than 32 bits, the receive data is automatically right-justified by the receive logic, with the upper bits of the receive FIFO zero-padded. You are responsible for making sure the transmit data is right-justified before writing into the transmit FIFO. The transmit logic ignores the upper unused bits when transmitting the data. For the field decode value, refer to Table 6-3 on page 101."]
940pub type DFS_32_A = DFS_A;
941#[doc = "Field `DFS_32` reader - Data Frame Size in 32-bit mode. Used to select the data frame size in 32-bit mode. These bits are only valid when SSI_MAX_XFER_SIZE is configured to 32. When the data frame size is programmed to be less than 32 bits, the receive data is automatically right-justified by the receive logic, with the upper bits of the receive FIFO zero-padded. You are responsible for making sure the transmit data is right-justified before writing into the transmit FIFO. The transmit logic ignores the upper unused bits when transmitting the data. For the field decode value, refer to Table 6-3 on page 101."]
942pub type DFS_32_R = DFS_R;
943impl R {
944    #[doc = "Bits 0:3 - Data Frame Size. Dependencies: When SSI_HC_FRF=1, SCPH bit is a read-only bit, with its value set by SSI_DFLT_SCPH. Selects the data frame length. When the data frame size is programmed to be less than 16 bits, the receive data are automatically right-justified by the receive logic, with the upper bits of the receive FIFO zero-padded. You must right-justify transmit data before writing into the transmit FIFO. The transmit logic ignores the upper unused bits when transmitting the data. For the field decode, refer to Table 6-2."]
945    #[inline(always)]
946    pub fn dfs(&self) -> DFS_R {
947        DFS_R::new((self.bits & 0x0f) as u8)
948    }
949    #[doc = "Bits 4:5 - 00 - Motorola SPI only"]
950    #[inline(always)]
951    pub fn frf(&self) -> FRF_R {
952        FRF_R::new(((self.bits >> 4) & 0x03) as u8)
953    }
954    #[doc = "Bit 6 - Serial Clock Phase. Valid when the frame format (FRF) is set to Motorola SPI. The serial clock phase selects the relationship of the serial clock with the slave select signal. When SCPH = 0, data are captured on the first edge of the serial clock. When SCPH = 1, the serial clock starts toggling one cycle after the slave select line is activated, and data are captured on the second edge of the serial clock. Dependencies: When SSI_HC_FRF=1, SCPH bit is a read-only bit, with its value set by SSI_DFLT_SCPH."]
955    #[inline(always)]
956    pub fn scph(&self) -> SCPH_R {
957        SCPH_R::new(((self.bits >> 6) & 0x01) != 0)
958    }
959    #[doc = "Bit 7 - Serial Clock Polarity. Valid when the frame format (FRF) is set to Motorola SPI. Used to select the polarity of the inactive serial clock, which is held inactive when the SPI Master is not actively transferring data on the serial bus. Dependencies: When SSI_HC_FRF=1, SCPOL bit is a read-only bit with its value set by SSI_DFLT_SCPOL."]
960    #[inline(always)]
961    pub fn scpol(&self) -> SCPOL_R {
962        SCPOL_R::new(((self.bits >> 7) & 0x01) != 0)
963    }
964    #[doc = "Bits 8:9 - Transfer Mode. Selects the mode of transfer for serial communication. This field does not affect the transfer duplicity. Only indicates whether the receive or transmit data are valid. In transmit-only mode, data received from the external device is not valid and is not stored in the receive FIFO memory; it is overwritten on the next transfer. In receive-only mode, transmitted data are not valid. After the first write to the transmit FIFO, the same word is retransmitted for the duration of the transfer. In transmit-and-receive mode, both transmit and receive data are valid. The transfer continues until the transmit FIFO is empty. Data received from the external device are stored into the receive FIFO memory, where it can be accessed by the host processor. In eeprom-read mode, receive data is not valid while control data is being transmitted. When all control data is sent to the EEPROM, receive data becomes valid and transmit data becomes invalid. All data in the transmit FIFO is considered control data in this mode. This transfer mode is only valid when the SPI Master is configured as a master device."]
965    #[inline(always)]
966    pub fn tmod(&self) -> TMOD_R {
967        TMOD_R::new(((self.bits >> 8) & 0x03) as u8)
968    }
969    #[doc = "Bit 10 - No function for SPI Master. Slave usage only."]
970    #[inline(always)]
971    pub fn slv_oe(&self) -> SLV_OE_R {
972        SLV_OE_R::new(((self.bits >> 10) & 0x01) != 0)
973    }
974    #[doc = "Bit 11 - Shift Register Loop. Used for testing purposes only. When internally active, connects the transmit shift register output to the receive shift register input. Can be used in both serial slave and serial-master modes. When the SPI Master is configured as a slave in loopback mode, the ss_in_n and ssi_clk signals must be provided by an external source. In this mode, the slave cannot generate these signals because there is nothing to which to loop back."]
975    #[inline(always)]
976    pub fn srl(&self) -> SRL_R {
977        SRL_R::new(((self.bits >> 11) & 0x01) != 0)
978    }
979    #[doc = "Bits 12:15 - Control Frame Size. Selects the length of the control word for the Microwire frame format. For the field decode, refer to Table 6-3 on page 101"]
980    #[inline(always)]
981    pub fn cfs(&self) -> CFS_R {
982        CFS_R::new(((self.bits >> 12) & 0x0f) as u8)
983    }
984    #[doc = "Bits 16:20 - Data Frame Size in 32-bit mode. Used to select the data frame size in 32-bit mode. These bits are only valid when SSI_MAX_XFER_SIZE is configured to 32. When the data frame size is programmed to be less than 32 bits, the receive data is automatically right-justified by the receive logic, with the upper bits of the receive FIFO zero-padded. You are responsible for making sure the transmit data is right-justified before writing into the transmit FIFO. The transmit logic ignores the upper unused bits when transmitting the data. For the field decode value, refer to Table 6-3 on page 101."]
985    #[inline(always)]
986    pub fn dfs_32(&self) -> DFS_32_R {
987        DFS_32_R::new(((self.bits >> 16) & 0x1f) as u8)
988    }
989}
990impl W {
991    #[doc = "Bits 0:3 - Data Frame Size. Dependencies: When SSI_HC_FRF=1, SCPH bit is a read-only bit, with its value set by SSI_DFLT_SCPH. Selects the data frame length. When the data frame size is programmed to be less than 16 bits, the receive data are automatically right-justified by the receive logic, with the upper bits of the receive FIFO zero-padded. You must right-justify transmit data before writing into the transmit FIFO. The transmit logic ignores the upper unused bits when transmitting the data. For the field decode, refer to Table 6-2."]
992    #[inline(always)]
993    pub fn dfs(&mut self) -> DFS_W {
994        DFS_W { w: self }
995    }
996    #[doc = "Bits 4:5 - 00 - Motorola SPI only"]
997    #[inline(always)]
998    pub fn frf(&mut self) -> FRF_W {
999        FRF_W { w: self }
1000    }
1001    #[doc = "Bit 6 - Serial Clock Phase. Valid when the frame format (FRF) is set to Motorola SPI. The serial clock phase selects the relationship of the serial clock with the slave select signal. When SCPH = 0, data are captured on the first edge of the serial clock. When SCPH = 1, the serial clock starts toggling one cycle after the slave select line is activated, and data are captured on the second edge of the serial clock. Dependencies: When SSI_HC_FRF=1, SCPH bit is a read-only bit, with its value set by SSI_DFLT_SCPH."]
1002    #[inline(always)]
1003    pub fn scph(&mut self) -> SCPH_W {
1004        SCPH_W { w: self }
1005    }
1006    #[doc = "Bit 7 - Serial Clock Polarity. Valid when the frame format (FRF) is set to Motorola SPI. Used to select the polarity of the inactive serial clock, which is held inactive when the SPI Master is not actively transferring data on the serial bus. Dependencies: When SSI_HC_FRF=1, SCPOL bit is a read-only bit with its value set by SSI_DFLT_SCPOL."]
1007    #[inline(always)]
1008    pub fn scpol(&mut self) -> SCPOL_W {
1009        SCPOL_W { w: self }
1010    }
1011    #[doc = "Bits 8:9 - Transfer Mode. Selects the mode of transfer for serial communication. This field does not affect the transfer duplicity. Only indicates whether the receive or transmit data are valid. In transmit-only mode, data received from the external device is not valid and is not stored in the receive FIFO memory; it is overwritten on the next transfer. In receive-only mode, transmitted data are not valid. After the first write to the transmit FIFO, the same word is retransmitted for the duration of the transfer. In transmit-and-receive mode, both transmit and receive data are valid. The transfer continues until the transmit FIFO is empty. Data received from the external device are stored into the receive FIFO memory, where it can be accessed by the host processor. In eeprom-read mode, receive data is not valid while control data is being transmitted. When all control data is sent to the EEPROM, receive data becomes valid and transmit data becomes invalid. All data in the transmit FIFO is considered control data in this mode. This transfer mode is only valid when the SPI Master is configured as a master device."]
1012    #[inline(always)]
1013    pub fn tmod(&mut self) -> TMOD_W {
1014        TMOD_W { w: self }
1015    }
1016    #[doc = "Bit 10 - No function for SPI Master. Slave usage only."]
1017    #[inline(always)]
1018    pub fn slv_oe(&mut self) -> SLV_OE_W {
1019        SLV_OE_W { w: self }
1020    }
1021    #[doc = "Bit 11 - Shift Register Loop. Used for testing purposes only. When internally active, connects the transmit shift register output to the receive shift register input. Can be used in both serial slave and serial-master modes. When the SPI Master is configured as a slave in loopback mode, the ss_in_n and ssi_clk signals must be provided by an external source. In this mode, the slave cannot generate these signals because there is nothing to which to loop back."]
1022    #[inline(always)]
1023    pub fn srl(&mut self) -> SRL_W {
1024        SRL_W { w: self }
1025    }
1026    #[doc = "Bits 12:15 - Control Frame Size. Selects the length of the control word for the Microwire frame format. For the field decode, refer to Table 6-3 on page 101"]
1027    #[inline(always)]
1028    pub fn cfs(&mut self) -> CFS_W {
1029        CFS_W { w: self }
1030    }
1031    #[doc = "Writes raw bits to the register."]
1032    #[inline(always)]
1033    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1034        self.0.bits(bits);
1035        self
1036    }
1037}
1038#[doc = "Control Register 0: This register controls the serial data transfer. It is impossible to write to this register when the SPI Master is enabled. The SPI Master is enabled and disabled by writing to the SSIENR register (0x008).\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlr0](index.html) module"]
1039pub struct CTRLR0_SPEC;
1040impl crate::RegisterSpec for CTRLR0_SPEC {
1041    type Ux = u32;
1042}
1043#[doc = "`read()` method returns [ctrlr0::R](R) reader structure"]
1044impl crate::Readable for CTRLR0_SPEC {
1045    type Reader = R;
1046}
1047#[doc = "`write(|w| ..)` method takes [ctrlr0::W](W) writer structure"]
1048impl crate::Writable for CTRLR0_SPEC {
1049    type Writer = W;
1050}
1051#[doc = "`reset()` method sets CTRLR0 to value 0"]
1052impl crate::Resettable for CTRLR0_SPEC {
1053    #[inline(always)]
1054    fn reset_value() -> Self::Ux {
1055        0
1056    }
1057}
eos_s3/spi/ctrlr0.rs

eos_s3/spi/
ctrlr0.rs
