1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "0x00 - On POR Reset Domain"]
5 pub misc_por_0: crate::Reg<misc_por_0::MISC_POR_0_SPEC>,
6 #[doc = "0x04 - On POR Reset Domain"]
7 pub misc_por_1: crate::Reg<misc_por_1::MISC_POR_1_SPEC>,
8 #[doc = "0x08 - On POR Reset Domain"]
9 pub misc_por_2: crate::Reg<misc_por_2::MISC_POR_2_SPEC>,
10 #[doc = "0x0c - On POR Reset Domain"]
11 pub misc_por_3: crate::Reg<misc_por_3::MISC_POR_3_SPEC>,
12 #[doc = "0x10 - Reserved"]
13 pub rst_ctrl_0: crate::Reg<rst_ctrl_0::RST_CTRL_0_SPEC>,
14 #[doc = "0x14 - Reserved"]
15 pub rst_ctrl_1: crate::Reg<rst_ctrl_1::RST_CTRL_1_SPEC>,
16 #[doc = "0x18 - Reserved"]
17 pub chip_sta_0: crate::Reg<chip_sta_0::CHIP_STA_0_SPEC>,
18 #[doc = "0x1c - Chip Status register"]
19 pub chip_sta_1: crate::Reg<chip_sta_1::CHIP_STA_1_SPEC>,
20 #[doc = "0x20 - Wake-up Interrupt Controller control register"]
21 pub wic_ctrl: crate::Reg<wic_ctrl::WIC_CTRL_SPEC>,
22 #[doc = "0x24 - Wake-up Interrupt Controller Status register"]
23 pub wic_status: crate::Reg<wic_status::WIC_STATUS_SPEC>,
24 _reserved10: [u8; 0x08],
25 #[doc = "0x30 - Power Down Scheme configuration"]
26 pub pwr_dwn_sch: crate::Reg<pwr_dwn_sch::PWR_DWN_SCH_SPEC>,
27 _reserved11: [u8; 0x0c],
28 #[doc = "0x40 - Control the power state of Oscillator once the M4 is in Power Saving Mode"]
29 pub pwr_off_osc: crate::Reg<pwr_off_osc::PWR_OFF_OSC_SPEC>,
30 #[doc = "0x44 - Configure the external wakeup event source. Turn on the OSC once PMUT is time out or GPIO INT is triggering."]
31 pub ext_waking_up_src:
32 crate::Reg<ext_waking_up_src::EXT_WAKING_UP_SRC_SPEC>,
33 _reserved13: [u8; 0x28],
34 #[doc = "0x70 - SDMA status register"]
35 pub sdma_status: crate::Reg<sdma_status::SDMA_STATUS_SPEC>,
36 #[doc = "0x74 - Register for SDMA Power Mode configuration"]
37 pub sdma_power_mode_cfg:
38 crate::Reg<sdma_power_mode_cfg::SDMA_POWER_MODE_CFG_SPEC>,
39 #[doc = "0x78 - Register for controlling if power down event will be masked"]
40 pub sdma_pd_src_mask_n:
41 crate::Reg<sdma_pd_src_mask_n::SDMA_PD_SRC_MASK_N_SPEC>,
42 #[doc = "0x7c - Reserved"]
43 pub sdma_wu_src_mask_n:
44 crate::Reg<sdma_wu_src_mask_n::SDMA_WU_SRC_MASK_N_SPEC>,
45 _reserved_17_m4_status: [u8; 0x04],
46 #[doc = "0x84 - Configuration for the M4 power domain"]
47 pub m4_pwr_mode_cfg: crate::Reg<m4_pwr_mode_cfg::M4_PWR_MODE_CFG_SPEC>,
48 #[doc = "0x88 - Reserved"]
49 pub m4_pd_src_maskk_n:
50 crate::Reg<m4_pd_src_maskk_n::M4_PD_SRC_MASKK_N_SPEC>,
51 #[doc = "0x8c - Reserved"]
52 pub m4_wu: crate::Reg<m4_wu::M4_WU_SPEC>,
53 #[doc = "0x90 - Status of the Flexible Fusion Engine"]
54 pub ffe_status: crate::Reg<ffe_status::FFE_STATUS_SPEC>,
55 #[doc = "0x94 - Power Mode configuration for the Flexible Fusion Engine Power Domain"]
56 pub ffe_pwr_mode_cfg: crate::Reg<ffe_pwr_mode_cfg::FFE_PWR_MODE_CFG_SPEC>,
57 #[doc = "0x98 - Control masking of busy signal. The falling edge of any of the above signals (non-mask) will put the FFE into Power saving mode base on the Power Mode Cfg. Note: These signals used to indicate the BUSY status, so they must be level signals."]
58 pub ffe_pd_src_mask_n:
59 crate::Reg<ffe_pd_src_mask_n::FFE_PD_SRC_MASK_N_SPEC>,
60 #[doc = "0x9c - Control the masking of the Flexible Fusion Engine wake-up event triggers"]
61 pub ffe_wu_src_mask_n:
62 crate::Reg<ffe_wu_src_mask_n::FFE_WU_SRC_MASK_N_SPEC>,
63 #[doc = "0xa0 - FPGA Fabric Power domain status"]
64 pub fb_status: crate::Reg<fb_status::FB_STATUS_SPEC>,
65 #[doc = "0xa4 - Power mode configuration for the FPGA Fabric Power domain"]
66 pub fb_pwr_mode_cfg: crate::Reg<fb_pwr_mode_cfg::FB_PWR_MODE_CFG_SPEC>,
67 #[doc = "0xa8 - Control masking of power down event signals for the FPGA Fabric power domain. The falling edge of any of the listed signals (non-mask) will put the FB into Power saving mode base on the Power Mode Cfg. Note: These signals used to indicate the BUSY status, so they must be level signals."]
68 pub fb_pd_src_mask_n: crate::Reg<fb_pd_src_mask_n::FB_PD_SRC_MASK_N_SPEC>,
69 #[doc = "0xac - Control the masking of the FPGA FAbric wake-up event triggers"]
70 pub fb_wu_src_mask_n: crate::Reg<fb_wu_src_mask_n::FB_WU_SRC_MASK_N_SPEC>,
71 _reserved29: [u8; 0x04],
72 #[doc = "0xb4 - Power mode configuration for the PF SRAM Power domain"]
73 pub pf_pwr_mode_cfg: crate::Reg<pf_pwr_mode_cfg::PF_PWR_MODE_CFG_SPEC>,
74 #[doc = "0xb8 - Reserved"]
75 pub pf_pd_src_mask_n: crate::Reg<pf_pd_src_mask_n::PF_PD_SRC_MASK_N_SPEC>,
76 #[doc = "0xbc - Reserved"]
77 pub pf_wu_src_mask_n: crate::Reg<pf_wu_src_mask_n::PF_WU_SRC_MASK_N_SPEC>,
78 #[doc = "0xc0 - M4S0 SRAM Power Domain status"]
79 pub m4s0_sram_status: crate::Reg<m4s0_sram_status::M4S0_SRAM_STATUS_SPEC>,
80 #[doc = "0xc4 - Power mode configuration for the M4S0 SRAM power domain"]
81 pub m4s0_pwr_mode_cfg:
82 crate::Reg<m4s0_pwr_mode_cfg::M4S0_PWR_MODE_CFG_SPEC>,
83 #[doc = "0xc8 - Control masking of power-down event triggers for the M4S0 SRAM domain"]
84 pub m4s0_pd_src_mask_n:
85 crate::Reg<m4s0_pd_src_mask_n::M4S0_PD_SRC_MASK_N_SPEC>,
86 #[doc = "0xcc - Control masking of wake-up event triggers for the M4S0 SRAM domain"]
87 pub m4s0_wu_src_mask_n:
88 crate::Reg<m4s0_wu_src_mask_n::M4S0_WU_SRC_MASK_N_SPEC>,
89 #[doc = "0xd0 - Status of the A1 power domain"]
90 pub a1_status: crate::Reg<a1_status::A1_STATUS_SPEC>,
91 #[doc = "0xd4 - Power mode configuration for the A1 power domain"]
92 pub a1_pwr_mode_cfg: crate::Reg<a1_pwr_mode_cfg::A1_PWR_MODE_CFG_SPEC>,
93 #[doc = "0xd8 - Reserved"]
94 pub a1_pd_src_mask_n: crate::Reg<a1_pd_src_mask_n::A1_PD_SRC_MASK_N_SPEC>,
95 #[doc = "0xdc - Control masking of wake-up event triggers for the A1 domain"]
96 pub a1_wu_src_mask_n: crate::Reg<a1_wu_src_mask_n::A1_WU_SRC_MASK_N_SPEC>,
97 #[doc = "0xe0 - I2S Power info"]
98 pub misc_status: crate::Reg<misc_status::MISC_STATUS_SPEC>,
99 #[doc = "0xe4 - Audio power domain status"]
100 pub audio_status: crate::Reg<audio_status::AUDIO_STATUS_SPEC>,
101 #[doc = "0xe8 - M4 SRAM Power domain status"]
102 pub m4_sram_status: crate::Reg<m4_sram_status::M4_SRAM_STATUS_SPEC>,
103 #[doc = "0xec - Control masking of wake-up event triggers for the Audio domains"]
104 pub audio_wu_src_mask_n:
105 crate::Reg<audio_wu_src_mask_n::AUDIO_WU_SRC_MASK_N_SPEC>,
106 _reserved44: [u8; 0x10],
107 #[doc = "0x100 - Control DS pins for different SRAM instances on the M4 subsystem. For each instance: 1'b1 : Enable the Deep Sleep funciton of SRAM Macro, Memory content will be kept. While M4 access the memory in Deep Sleep mode, the HW will clear the corresponding bit."]
108 pub m4_mem_ctrl_0: crate::Reg<m4_mem_ctrl_0::M4_MEM_CTRL_0_SPEC>,
109 #[doc = "0x104 - Control Shutdown pin for various instances of SRAM on the M4 subsystem. For each instance: 1'b1 : Enable the Shutdown funciton of SRAM Macro, Memory content will be lost. While M4 access the memory in Shutdown mode, the HW will clear the corresponding bit."]
110 pub m4_mem_ctrl_1: crate::Reg<m4_mem_ctrl_1::M4_MEM_CTRL_1_SPEC>,
111 #[doc = "0x108 - RESERVED"]
112 pub pf_mem_ctrl_0: crate::Reg<pf_mem_ctrl_0::PF_MEM_CTRL_0_SPEC>,
113 #[doc = "0x10c - Control Shut Down pin of various FIFOs intances in the PF subsystem. For each one: 1'b1 : Enable the Shut Down function of SRAM Macro, Memory content will be lost"]
114 pub pf_mem_ctrl_1: crate::Reg<pf_mem_ctrl_1::PF_MEM_CTRL_1_SPEC>,
115 #[doc = "0x110 - Control the Deep Sleep pin of various elements in the Flexible Fusion Engine power domain. For each: 1'b1 : Enable the Deep Sleep function of SRAM Macro, Memory content will be kept."]
116 pub ffe_mem_ctrl_0: crate::Reg<ffe_mem_ctrl_0::FFE_MEM_CTRL_0_SPEC>,
117 #[doc = "0x114 - Control the Shut Down pin of various elements in the Flexible Fusion Engine power domain. For each: 1'b1 : Enable the Deep Sleep function of SRAM Macro, Memory content will be kept."]
118 pub ffe_mem_ctrl_1: crate::Reg<ffe_mem_ctrl_1::FFE_MEM_CTRL_1_SPEC>,
119 #[doc = "0x118 - Control the Deep Sleep pin of Audio channels. For each: 1'b1 : Enable the Deep Sleep function of SRAM Macro, Memory content will be kept."]
120 pub audio_mem_ctrl_0: crate::Reg<audio_mem_ctrl_0::AUDIO_MEM_CTRL_0_SPEC>,
121 #[doc = "0x11c - Control the shut down pin of Audio channels. For each: 1'b1 : Enable the Deep Sleep function of SRAM Macro, Memory content will be kept."]
122 pub audio_mem_ctrl_1: crate::Reg<audio_mem_ctrl_1::AUDIO_MEM_CTRL_1_SPEC>,
123 #[doc = "0x120 - Reserved"]
124 pub m4_mem_cfg: crate::Reg<m4_mem_cfg::M4_MEM_CFG_SPEC>,
125 #[doc = "0x124 - Reserved"]
126 pub pf_mem_cfg: crate::Reg<pf_mem_cfg::PF_MEM_CFG_SPEC>,
127 #[doc = "0x128 - Control Light Sleep pin of different FFE SRAM power domains"]
128 pub ffe_mem_cfg: crate::Reg<ffe_mem_cfg::FFE_MEM_CFG_SPEC>,
129 #[doc = "0x12c - Reserved"]
130 pub audio_mem_cfg: crate::Reg<audio_mem_cfg::AUDIO_MEM_CFG_SPEC>,
131 #[doc = "0x130 - Reserved"]
132 pub m4_mem_ctrl_pwr_0:
133 crate::Reg<m4_mem_ctrl_pwr_0::M4_MEM_CTRL_PWR_0_SPEC>,
134 #[doc = "0x134 - Reserved"]
135 pub m4_mem_ctrl_pwr_1:
136 crate::Reg<m4_mem_ctrl_pwr_1::M4_MEM_CTRL_PWR_1_SPEC>,
137 #[doc = "0x138 - Reserved"]
138 pub m4_mem_ctrl_pwr_2:
139 crate::Reg<m4_mem_ctrl_pwr_2::M4_MEM_CTRL_PWR_2_SPEC>,
140 _reserved59: [u8; 0x04],
141 #[doc = "0x140 - Control the Deep Sleep function of SRAM Macro for the SDMA power domain"]
142 pub sdma_mem_ctrl_0: crate::Reg<sdma_mem_ctrl_0::SDMA_MEM_CTRL_0_SPEC>,
143 #[doc = "0x144 - Control the Shut Down function of SRAM Macro for the SDMA power domain"]
144 pub sdma_mem_ctrl_1: crate::Reg<sdma_mem_ctrl_1::SDMA_MEM_CTRL_1_SPEC>,
145 _reserved61: [u8; 0x38],
146 #[doc = "0x180 - Memory Power Down Control"]
147 pub mem_pwr_dwn_ctrl: crate::Reg<mem_pwr_dwn_ctrl::MEM_PWR_DWN_CTRL_SPEC>,
148 #[doc = "0x184 - Configuration for the PMU timer time-out period"]
149 pub pmu_timer_cfg_0: crate::Reg<pmu_timer_cfg_0::PMU_TIMER_CFG_0_SPEC>,
150 #[doc = "0x188 - Control wether the PMU timer is enabled or disabled"]
151 pub pmu_timer_cfg_1: crate::Reg<pmu_timer_cfg_1::PMU_TIMER_CFG_1_SPEC>,
152 #[doc = "0x18c - Control the delay for power-on after wake-up event. Applies to all power domains"]
153 pub pdwu_timer_cfg: crate::Reg<pdwu_timer_cfg::PDWU_TIMER_CFG_SPEC>,
154 _reserved65: [u8; 0x70],
155 #[doc = "0x200 - Registers for triggering power-down events in the FFE, FB and PF power domains."]
156 pub ffe_fb_pf_sw_pd: crate::Reg<ffe_fb_pf_sw_pd::FFE_FB_PF_SW_PD_SPEC>,
157 #[doc = "0x204 - Register for triggering power-down events in M4 SRAM power domains. (RWHC)"]
158 pub m4_sram_sw_pd: crate::Reg<m4_sram_sw_pd::M4_SRAM_SW_PD_SPEC>,
159 #[doc = "0x208 - Register for triggering power down events in MISC power domains + some general purpose SFR's (RWHC)"]
160 pub misc_sw_pd: crate::Reg<misc_sw_pd::MISC_SW_PD_SPEC>,
161 #[doc = "0x20c - Register for triggering power-down events in Audio power domains. (RWHC)"]
162 pub audio_sw_pd: crate::Reg<audio_sw_pd::AUDIO_SW_PD_SPEC>,
163 #[doc = "0x210 - Registers for triggering wake-up events in the FFE, FB and PF power domains."]
164 pub ffe_fb_pf_sw_wu: crate::Reg<ffe_fb_pf_sw_wu::FFE_FB_PF_SW_WU_SPEC>,
165 #[doc = "0x214 - Register for triggering wake-up events in M4 SRAM power domains. (RWHC)"]
166 pub m4_sram_sw_wu: crate::Reg<m4_sram_sw_wu::M4_SRAM_SW_WU_SPEC>,
167 #[doc = "0x218 - Register for triggering wake up events in MISC power domains + some general purpose SFR's (RWHC)"]
168 pub misc_sw_wu: crate::Reg<misc_sw_wu::MISC_SW_WU_SPEC>,
169 #[doc = "0x21c - Register for triggering wake-up events in Audio power domains. (RWHC)"]
170 pub audio_sram_sw_wu: crate::Reg<audio_sram_sw_wu::AUDIO_SRAM_SW_WU_SPEC>,
171 #[doc = "0x220 - Power Management Unit Software Test Mode priority control"]
172 pub pmu_stm_priority: crate::Reg<pmu_stm_priority::PMU_STM_PRIORITY_SPEC>,
173 _reserved74: [u8; 0x0c],
174 #[doc = "0x230 - Control for M4SRAM power domain light sleep mode"]
175 pub m4sram_ssw_lpmf: crate::Reg<m4sram_ssw_lpmf::M4SRAM_SSW_LPMF_SPEC>,
176 #[doc = "0x234 - Control masking for the LPMH (Low Power Mode header - deep sleep circuit)"]
177 pub m4sram_ssw_lpmh_mask_n:
178 crate::Reg<m4sram_ssw_lpmh_mask_n::M4SRAM_SSW_LPMH_MASK_N_SPEC>,
179 _reserved76: [u8; 0x01b0],
180 #[doc = "0x3e8 - Configuration for the amount of IDLE cycles before powering on the FB domain"]
181 pub fbvlpmin_width: crate::Reg<fbvlpmin_width::FBVLPMINWIDTH_SPEC>,
182 #[doc = "0x3ec - Indicates if AP nees to reload the code to SRAM"]
183 pub apreboot_status: crate::Reg<apreboot_status::APREBOOTSTATUS_SPEC>,
184 _reserved_78_fb_isolation: [u8; 0x08],
185}
186impl RegisterBlock {
187 #[doc = "0x80 - PF SRAM Power Domain status"]
188 #[inline(always)]
189 pub fn pf_status(&self) -> &crate::Reg<pf_status::PF_STATUS_SPEC> {
190 unsafe {
191 &*(((self as *const Self) as *const u8).add(128usize)
192 as *const crate::Reg<pf_status::PF_STATUS_SPEC>)
193 }
194 }
195 #[doc = "0x80 - Status of the M4 Power Domain"]
196 #[inline(always)]
197 pub fn m4_status(&self) -> &crate::Reg<m4_status::M4_STATUS_SPEC> {
198 unsafe {
199 &*(((self as *const Self) as *const u8).add(128usize)
200 as *const crate::Reg<m4_status::M4_STATUS_SPEC>)
201 }
202 }
203 #[doc = "0x3f0 - Configure FB config enable and wether Audio SRAM can be put into Deep Sleep by the Audio hardware"]
204 #[inline(always)]
205 pub fn gen_purpose_0(
206 &self,
207 ) -> &crate::Reg<gen_purpose_0::GEN_PURPOSE_0_SPEC> {
208 unsafe {
209 &*(((self as *const Self) as *const u8).add(1008usize)
210 as *const crate::Reg<gen_purpose_0::GEN_PURPOSE_0_SPEC>)
211 }
212 }
213 #[doc = "0x3f3 - Control for: Wether ext-interrupt can be used to wake up FFE, and clock switching for FFE/M4 power domains"]
214 #[inline(always)]
215 pub fn gen_purpose_1(
216 &self,
217 ) -> &crate::Reg<gen_purpose_1::GEN_PURPOSE_1_SPEC> {
218 unsafe {
219 &*(((self as *const Self) as *const u8).add(1011usize)
220 as *const crate::Reg<gen_purpose_1::GEN_PURPOSE_1_SPEC>)
221 }
222 }
223 #[doc = "0x3f4 - Control the FB Isolation"]
224 #[inline(always)]
225 pub fn fb_isolation(&self) -> &crate::Reg<fb_isolation::FB_ISOLATION_SPEC> {
226 unsafe {
227 &*(((self as *const Self) as *const u8).add(1012usize)
228 as *const crate::Reg<fb_isolation::FB_ISOLATION_SPEC>)
229 }
230 }
231}
232#[doc = "MISC_POR_0 register accessor: an alias for `Reg<MISC_POR_0_SPEC>`"]
233pub type MISC_POR_0 = crate::Reg<misc_por_0::MISC_POR_0_SPEC>;
234#[doc = "On POR Reset Domain"]
235pub mod misc_por_0;
236#[doc = "MISC_POR_1 register accessor: an alias for `Reg<MISC_POR_1_SPEC>`"]
237pub type MISC_POR_1 = crate::Reg<misc_por_1::MISC_POR_1_SPEC>;
238#[doc = "On POR Reset Domain"]
239pub mod misc_por_1;
240#[doc = "MISC_POR_2 register accessor: an alias for `Reg<MISC_POR_2_SPEC>`"]
241pub type MISC_POR_2 = crate::Reg<misc_por_2::MISC_POR_2_SPEC>;
242#[doc = "On POR Reset Domain"]
243pub mod misc_por_2;
244#[doc = "MISC_POR_3 register accessor: an alias for `Reg<MISC_POR_3_SPEC>`"]
245pub type MISC_POR_3 = crate::Reg<misc_por_3::MISC_POR_3_SPEC>;
246#[doc = "On POR Reset Domain"]
247pub mod misc_por_3;
248#[doc = "RST_CTRL_0 register accessor: an alias for `Reg<RST_CTRL_0_SPEC>`"]
249pub type RST_CTRL_0 = crate::Reg<rst_ctrl_0::RST_CTRL_0_SPEC>;
250#[doc = "Reserved"]
251pub mod rst_ctrl_0;
252#[doc = "RST_CTRL_1 register accessor: an alias for `Reg<RST_CTRL_1_SPEC>`"]
253pub type RST_CTRL_1 = crate::Reg<rst_ctrl_1::RST_CTRL_1_SPEC>;
254#[doc = "Reserved"]
255pub mod rst_ctrl_1;
256#[doc = "CHIP_STA_0 register accessor: an alias for `Reg<CHIP_STA_0_SPEC>`"]
257pub type CHIP_STA_0 = crate::Reg<chip_sta_0::CHIP_STA_0_SPEC>;
258#[doc = "Reserved"]
259pub mod chip_sta_0;
260#[doc = "CHIP_STA_1 register accessor: an alias for `Reg<CHIP_STA_1_SPEC>`"]
261pub type CHIP_STA_1 = crate::Reg<chip_sta_1::CHIP_STA_1_SPEC>;
262#[doc = "Chip Status register"]
263pub mod chip_sta_1;
264#[doc = "WIC_CTRL register accessor: an alias for `Reg<WIC_CTRL_SPEC>`"]
265pub type WIC_CTRL = crate::Reg<wic_ctrl::WIC_CTRL_SPEC>;
266#[doc = "Wake-up Interrupt Controller control register"]
267pub mod wic_ctrl;
268#[doc = "WIC_STATUS register accessor: an alias for `Reg<WIC_STATUS_SPEC>`"]
269pub type WIC_STATUS = crate::Reg<wic_status::WIC_STATUS_SPEC>;
270#[doc = "Wake-up Interrupt Controller Status register"]
271pub mod wic_status;
272#[doc = "PWR_DWN_SCH register accessor: an alias for `Reg<PWR_DWN_SCH_SPEC>`"]
273pub type PWR_DWN_SCH = crate::Reg<pwr_dwn_sch::PWR_DWN_SCH_SPEC>;
274#[doc = "Power Down Scheme configuration"]
275pub mod pwr_dwn_sch;
276#[doc = "PWR_OFF_OSC register accessor: an alias for `Reg<PWR_OFF_OSC_SPEC>`"]
277pub type PWR_OFF_OSC = crate::Reg<pwr_off_osc::PWR_OFF_OSC_SPEC>;
278#[doc = "Control the power state of Oscillator once the M4 is in Power Saving Mode"]
279pub mod pwr_off_osc;
280#[doc = "EXT_WAKING_UP_SRC register accessor: an alias for `Reg<EXT_WAKING_UP_SRC_SPEC>`"]
281pub type EXT_WAKING_UP_SRC =
282 crate::Reg<ext_waking_up_src::EXT_WAKING_UP_SRC_SPEC>;
283#[doc = "Configure the external wakeup event source. Turn on the OSC once PMUT is time out or GPIO INT is triggering."]
284pub mod ext_waking_up_src;
285#[doc = "SDMA_STATUS register accessor: an alias for `Reg<SDMA_STATUS_SPEC>`"]
286pub type SDMA_STATUS = crate::Reg<sdma_status::SDMA_STATUS_SPEC>;
287#[doc = "SDMA status register"]
288pub mod sdma_status;
289#[doc = "SDMA_POWER_MODE_CFG register accessor: an alias for `Reg<SDMA_POWER_MODE_CFG_SPEC>`"]
290pub type SDMA_POWER_MODE_CFG =
291 crate::Reg<sdma_power_mode_cfg::SDMA_POWER_MODE_CFG_SPEC>;
292#[doc = "Register for SDMA Power Mode configuration"]
293pub mod sdma_power_mode_cfg;
294#[doc = "SDMA_PD_SRC_MASK_N register accessor: an alias for `Reg<SDMA_PD_SRC_MASK_N_SPEC>`"]
295pub type SDMA_PD_SRC_MASK_N =
296 crate::Reg<sdma_pd_src_mask_n::SDMA_PD_SRC_MASK_N_SPEC>;
297#[doc = "Register for controlling if power down event will be masked"]
298pub mod sdma_pd_src_mask_n;
299#[doc = "SDMA_WU_SRC_MASK_N register accessor: an alias for `Reg<SDMA_WU_SRC_MASK_N_SPEC>`"]
300pub type SDMA_WU_SRC_MASK_N =
301 crate::Reg<sdma_wu_src_mask_n::SDMA_WU_SRC_MASK_N_SPEC>;
302#[doc = "Reserved"]
303pub mod sdma_wu_src_mask_n;
304#[doc = "M4_STATUS register accessor: an alias for `Reg<M4_STATUS_SPEC>`"]
305pub type M4_STATUS = crate::Reg<m4_status::M4_STATUS_SPEC>;
306#[doc = "Status of the M4 Power Domain"]
307pub mod m4_status;
308#[doc = "M4_PWR_MODE_CFG register accessor: an alias for `Reg<M4_PWR_MODE_CFG_SPEC>`"]
309pub type M4_PWR_MODE_CFG = crate::Reg<m4_pwr_mode_cfg::M4_PWR_MODE_CFG_SPEC>;
310#[doc = "Configuration for the M4 power domain"]
311pub mod m4_pwr_mode_cfg;
312#[doc = "M4_PD_SRC_MASKk_N register accessor: an alias for `Reg<M4_PD_SRC_MASKK_N_SPEC>`"]
313pub type M4_PD_SRC_MASKK_N =
314 crate::Reg<m4_pd_src_maskk_n::M4_PD_SRC_MASKK_N_SPEC>;
315#[doc = "Reserved"]
316pub mod m4_pd_src_maskk_n;
317#[doc = "M4_WU register accessor: an alias for `Reg<M4_WU_SPEC>`"]
318pub type M4_WU = crate::Reg<m4_wu::M4_WU_SPEC>;
319#[doc = "Reserved"]
320pub mod m4_wu;
321#[doc = "FFE_STATUS register accessor: an alias for `Reg<FFE_STATUS_SPEC>`"]
322pub type FFE_STATUS = crate::Reg<ffe_status::FFE_STATUS_SPEC>;
323#[doc = "Status of the Flexible Fusion Engine"]
324pub mod ffe_status;
325#[doc = "FFE_PWR_MODE_CFG register accessor: an alias for `Reg<FFE_PWR_MODE_CFG_SPEC>`"]
326pub type FFE_PWR_MODE_CFG = crate::Reg<ffe_pwr_mode_cfg::FFE_PWR_MODE_CFG_SPEC>;
327#[doc = "Power Mode configuration for the Flexible Fusion Engine Power Domain"]
328pub mod ffe_pwr_mode_cfg;
329#[doc = "FFE_PD_SRC_MASK_N register accessor: an alias for `Reg<FFE_PD_SRC_MASK_N_SPEC>`"]
330pub type FFE_PD_SRC_MASK_N =
331 crate::Reg<ffe_pd_src_mask_n::FFE_PD_SRC_MASK_N_SPEC>;
332#[doc = "Control masking of busy signal. The falling edge of any of the above signals (non-mask) will put the FFE into Power saving mode base on the Power Mode Cfg. Note: These signals used to indicate the BUSY status, so they must be level signals."]
333pub mod ffe_pd_src_mask_n;
334#[doc = "FFE_WU_SRC_MASK_N register accessor: an alias for `Reg<FFE_WU_SRC_MASK_N_SPEC>`"]
335pub type FFE_WU_SRC_MASK_N =
336 crate::Reg<ffe_wu_src_mask_n::FFE_WU_SRC_MASK_N_SPEC>;
337#[doc = "Control the masking of the Flexible Fusion Engine wake-up event triggers"]
338pub mod ffe_wu_src_mask_n;
339#[doc = "FB_STATUS register accessor: an alias for `Reg<FB_STATUS_SPEC>`"]
340pub type FB_STATUS = crate::Reg<fb_status::FB_STATUS_SPEC>;
341#[doc = "FPGA Fabric Power domain status"]
342pub mod fb_status;
343#[doc = "FB_PWR_MODE_CFG register accessor: an alias for `Reg<FB_PWR_MODE_CFG_SPEC>`"]
344pub type FB_PWR_MODE_CFG = crate::Reg<fb_pwr_mode_cfg::FB_PWR_MODE_CFG_SPEC>;
345#[doc = "Power mode configuration for the FPGA Fabric Power domain"]
346pub mod fb_pwr_mode_cfg;
347#[doc = "FB_PD_SRC_MASK_N register accessor: an alias for `Reg<FB_PD_SRC_MASK_N_SPEC>`"]
348pub type FB_PD_SRC_MASK_N = crate::Reg<fb_pd_src_mask_n::FB_PD_SRC_MASK_N_SPEC>;
349#[doc = "Control masking of power down event signals for the FPGA Fabric power domain. The falling edge of any of the listed signals (non-mask) will put the FB into Power saving mode base on the Power Mode Cfg. Note: These signals used to indicate the BUSY status, so they must be level signals."]
350pub mod fb_pd_src_mask_n;
351#[doc = "FB_WU_SRC_MASK_N register accessor: an alias for `Reg<FB_WU_SRC_MASK_N_SPEC>`"]
352pub type FB_WU_SRC_MASK_N = crate::Reg<fb_wu_src_mask_n::FB_WU_SRC_MASK_N_SPEC>;
353#[doc = "Control the masking of the FPGA FAbric wake-up event triggers"]
354pub mod fb_wu_src_mask_n;
355#[doc = "PF_STATUS register accessor: an alias for `Reg<PF_STATUS_SPEC>`"]
356pub type PF_STATUS = crate::Reg<pf_status::PF_STATUS_SPEC>;
357#[doc = "PF SRAM Power Domain status"]
358pub mod pf_status;
359#[doc = "PF_PWR_MODE_CFG register accessor: an alias for `Reg<PF_PWR_MODE_CFG_SPEC>`"]
360pub type PF_PWR_MODE_CFG = crate::Reg<pf_pwr_mode_cfg::PF_PWR_MODE_CFG_SPEC>;
361#[doc = "Power mode configuration for the PF SRAM Power domain"]
362pub mod pf_pwr_mode_cfg;
363#[doc = "PF_PD_SRC_MASK_N register accessor: an alias for `Reg<PF_PD_SRC_MASK_N_SPEC>`"]
364pub type PF_PD_SRC_MASK_N = crate::Reg<pf_pd_src_mask_n::PF_PD_SRC_MASK_N_SPEC>;
365#[doc = "Reserved"]
366pub mod pf_pd_src_mask_n;
367#[doc = "PF_WU_SRC_MASK_N register accessor: an alias for `Reg<PF_WU_SRC_MASK_N_SPEC>`"]
368pub type PF_WU_SRC_MASK_N = crate::Reg<pf_wu_src_mask_n::PF_WU_SRC_MASK_N_SPEC>;
369#[doc = "Reserved"]
370pub mod pf_wu_src_mask_n;
371#[doc = "M4S0_SRAM_STATUS register accessor: an alias for `Reg<M4S0_SRAM_STATUS_SPEC>`"]
372pub type M4S0_SRAM_STATUS = crate::Reg<m4s0_sram_status::M4S0_SRAM_STATUS_SPEC>;
373#[doc = "M4S0 SRAM Power Domain status"]
374pub mod m4s0_sram_status;
375#[doc = "M4S0_PWR_MODE_CFG register accessor: an alias for `Reg<M4S0_PWR_MODE_CFG_SPEC>`"]
376pub type M4S0_PWR_MODE_CFG =
377 crate::Reg<m4s0_pwr_mode_cfg::M4S0_PWR_MODE_CFG_SPEC>;
378#[doc = "Power mode configuration for the M4S0 SRAM power domain"]
379pub mod m4s0_pwr_mode_cfg;
380#[doc = "M4S0_PD_SRC_MASK_N register accessor: an alias for `Reg<M4S0_PD_SRC_MASK_N_SPEC>`"]
381pub type M4S0_PD_SRC_MASK_N =
382 crate::Reg<m4s0_pd_src_mask_n::M4S0_PD_SRC_MASK_N_SPEC>;
383#[doc = "Control masking of power-down event triggers for the M4S0 SRAM domain"]
384pub mod m4s0_pd_src_mask_n;
385#[doc = "M4S0_WU_SRC_MASK_N register accessor: an alias for `Reg<M4S0_WU_SRC_MASK_N_SPEC>`"]
386pub type M4S0_WU_SRC_MASK_N =
387 crate::Reg<m4s0_wu_src_mask_n::M4S0_WU_SRC_MASK_N_SPEC>;
388#[doc = "Control masking of wake-up event triggers for the M4S0 SRAM domain"]
389pub mod m4s0_wu_src_mask_n;
390#[doc = "A1_STATUS register accessor: an alias for `Reg<A1_STATUS_SPEC>`"]
391pub type A1_STATUS = crate::Reg<a1_status::A1_STATUS_SPEC>;
392#[doc = "Status of the A1 power domain"]
393pub mod a1_status;
394#[doc = "A1_PWR_MODE_CFG register accessor: an alias for `Reg<A1_PWR_MODE_CFG_SPEC>`"]
395pub type A1_PWR_MODE_CFG = crate::Reg<a1_pwr_mode_cfg::A1_PWR_MODE_CFG_SPEC>;
396#[doc = "Power mode configuration for the A1 power domain"]
397pub mod a1_pwr_mode_cfg;
398#[doc = "A1_PD_SRC_MASK_N register accessor: an alias for `Reg<A1_PD_SRC_MASK_N_SPEC>`"]
399pub type A1_PD_SRC_MASK_N = crate::Reg<a1_pd_src_mask_n::A1_PD_SRC_MASK_N_SPEC>;
400#[doc = "Reserved"]
401pub mod a1_pd_src_mask_n;
402#[doc = "A1_WU_SRC_MASK_N register accessor: an alias for `Reg<A1_WU_SRC_MASK_N_SPEC>`"]
403pub type A1_WU_SRC_MASK_N = crate::Reg<a1_wu_src_mask_n::A1_WU_SRC_MASK_N_SPEC>;
404#[doc = "Control masking of wake-up event triggers for the A1 domain"]
405pub mod a1_wu_src_mask_n;
406#[doc = "MISC_STATUS register accessor: an alias for `Reg<MISC_STATUS_SPEC>`"]
407pub type MISC_STATUS = crate::Reg<misc_status::MISC_STATUS_SPEC>;
408#[doc = "I2S Power info"]
409pub mod misc_status;
410#[doc = "AUDIO_STATUS register accessor: an alias for `Reg<AUDIO_STATUS_SPEC>`"]
411pub type AUDIO_STATUS = crate::Reg<audio_status::AUDIO_STATUS_SPEC>;
412#[doc = "Audio power domain status"]
413pub mod audio_status;
414#[doc = "M4_SRAM_STATUS register accessor: an alias for `Reg<M4_SRAM_STATUS_SPEC>`"]
415pub type M4_SRAM_STATUS = crate::Reg<m4_sram_status::M4_SRAM_STATUS_SPEC>;
416#[doc = "M4 SRAM Power domain status"]
417pub mod m4_sram_status;
418#[doc = "AUDIO_WU_SRC_MASK_N register accessor: an alias for `Reg<AUDIO_WU_SRC_MASK_N_SPEC>`"]
419pub type AUDIO_WU_SRC_MASK_N =
420 crate::Reg<audio_wu_src_mask_n::AUDIO_WU_SRC_MASK_N_SPEC>;
421#[doc = "Control masking of wake-up event triggers for the Audio domains"]
422pub mod audio_wu_src_mask_n;
423#[doc = "M4_MEM_CTRL_0 register accessor: an alias for `Reg<M4_MEM_CTRL_0_SPEC>`"]
424pub type M4_MEM_CTRL_0 = crate::Reg<m4_mem_ctrl_0::M4_MEM_CTRL_0_SPEC>;
425#[doc = "Control DS pins for different SRAM instances on the M4 subsystem. For each instance: 1'b1 : Enable the Deep Sleep funciton of SRAM Macro, Memory content will be kept. While M4 access the memory in Deep Sleep mode, the HW will clear the corresponding bit."]
426pub mod m4_mem_ctrl_0;
427#[doc = "M4_MEM_CTRL_1 register accessor: an alias for `Reg<M4_MEM_CTRL_1_SPEC>`"]
428pub type M4_MEM_CTRL_1 = crate::Reg<m4_mem_ctrl_1::M4_MEM_CTRL_1_SPEC>;
429#[doc = "Control Shutdown pin for various instances of SRAM on the M4 subsystem. For each instance: 1'b1 : Enable the Shutdown funciton of SRAM Macro, Memory content will be lost. While M4 access the memory in Shutdown mode, the HW will clear the corresponding bit."]
430pub mod m4_mem_ctrl_1;
431#[doc = "PF_MEM_CTRL_0 register accessor: an alias for `Reg<PF_MEM_CTRL_0_SPEC>`"]
432pub type PF_MEM_CTRL_0 = crate::Reg<pf_mem_ctrl_0::PF_MEM_CTRL_0_SPEC>;
433#[doc = "RESERVED"]
434pub mod pf_mem_ctrl_0;
435#[doc = "PF_MEM_CTRL_1 register accessor: an alias for `Reg<PF_MEM_CTRL_1_SPEC>`"]
436pub type PF_MEM_CTRL_1 = crate::Reg<pf_mem_ctrl_1::PF_MEM_CTRL_1_SPEC>;
437#[doc = "Control Shut Down pin of various FIFOs intances in the PF subsystem. For each one: 1'b1 : Enable the Shut Down function of SRAM Macro, Memory content will be lost"]
438pub mod pf_mem_ctrl_1;
439#[doc = "FFE_MEM_CTRL_0 register accessor: an alias for `Reg<FFE_MEM_CTRL_0_SPEC>`"]
440pub type FFE_MEM_CTRL_0 = crate::Reg<ffe_mem_ctrl_0::FFE_MEM_CTRL_0_SPEC>;
441#[doc = "Control the Deep Sleep pin of various elements in the Flexible Fusion Engine power domain. For each: 1'b1 : Enable the Deep Sleep function of SRAM Macro, Memory content will be kept."]
442pub mod ffe_mem_ctrl_0;
443#[doc = "FFE_MEM_CTRL_1 register accessor: an alias for `Reg<FFE_MEM_CTRL_1_SPEC>`"]
444pub type FFE_MEM_CTRL_1 = crate::Reg<ffe_mem_ctrl_1::FFE_MEM_CTRL_1_SPEC>;
445#[doc = "Control the Shut Down pin of various elements in the Flexible Fusion Engine power domain. For each: 1'b1 : Enable the Deep Sleep function of SRAM Macro, Memory content will be kept."]
446pub mod ffe_mem_ctrl_1;
447#[doc = "AUDIO_MEM_CTRL_0 register accessor: an alias for `Reg<AUDIO_MEM_CTRL_0_SPEC>`"]
448pub type AUDIO_MEM_CTRL_0 = crate::Reg<audio_mem_ctrl_0::AUDIO_MEM_CTRL_0_SPEC>;
449#[doc = "Control the Deep Sleep pin of Audio channels. For each: 1'b1 : Enable the Deep Sleep function of SRAM Macro, Memory content will be kept."]
450pub mod audio_mem_ctrl_0;
451#[doc = "AUDIO_MEM_CTRL_1 register accessor: an alias for `Reg<AUDIO_MEM_CTRL_1_SPEC>`"]
452pub type AUDIO_MEM_CTRL_1 = crate::Reg<audio_mem_ctrl_1::AUDIO_MEM_CTRL_1_SPEC>;
453#[doc = "Control the shut down pin of Audio channels. For each: 1'b1 : Enable the Deep Sleep function of SRAM Macro, Memory content will be kept."]
454pub mod audio_mem_ctrl_1;
455#[doc = "M4_MEM_CFG register accessor: an alias for `Reg<M4_MEM_CFG_SPEC>`"]
456pub type M4_MEM_CFG = crate::Reg<m4_mem_cfg::M4_MEM_CFG_SPEC>;
457#[doc = "Reserved"]
458pub mod m4_mem_cfg;
459#[doc = "PF_MEM_CFG register accessor: an alias for `Reg<PF_MEM_CFG_SPEC>`"]
460pub type PF_MEM_CFG = crate::Reg<pf_mem_cfg::PF_MEM_CFG_SPEC>;
461#[doc = "Reserved"]
462pub mod pf_mem_cfg;
463#[doc = "FFE_MEM_CFG register accessor: an alias for `Reg<FFE_MEM_CFG_SPEC>`"]
464pub type FFE_MEM_CFG = crate::Reg<ffe_mem_cfg::FFE_MEM_CFG_SPEC>;
465#[doc = "Control Light Sleep pin of different FFE SRAM power domains"]
466pub mod ffe_mem_cfg;
467#[doc = "AUDIO_MEM_CFG register accessor: an alias for `Reg<AUDIO_MEM_CFG_SPEC>`"]
468pub type AUDIO_MEM_CFG = crate::Reg<audio_mem_cfg::AUDIO_MEM_CFG_SPEC>;
469#[doc = "Reserved"]
470pub mod audio_mem_cfg;
471#[doc = "M4_MEM_CTRL_PWR_0 register accessor: an alias for `Reg<M4_MEM_CTRL_PWR_0_SPEC>`"]
472pub type M4_MEM_CTRL_PWR_0 =
473 crate::Reg<m4_mem_ctrl_pwr_0::M4_MEM_CTRL_PWR_0_SPEC>;
474#[doc = "Reserved"]
475pub mod m4_mem_ctrl_pwr_0;
476#[doc = "M4_MEM_CTRL_PWR_1 register accessor: an alias for `Reg<M4_MEM_CTRL_PWR_1_SPEC>`"]
477pub type M4_MEM_CTRL_PWR_1 =
478 crate::Reg<m4_mem_ctrl_pwr_1::M4_MEM_CTRL_PWR_1_SPEC>;
479#[doc = "Reserved"]
480pub mod m4_mem_ctrl_pwr_1;
481#[doc = "M4_MEM_CTRL_PWR_2 register accessor: an alias for `Reg<M4_MEM_CTRL_PWR_2_SPEC>`"]
482pub type M4_MEM_CTRL_PWR_2 =
483 crate::Reg<m4_mem_ctrl_pwr_2::M4_MEM_CTRL_PWR_2_SPEC>;
484#[doc = "Reserved"]
485pub mod m4_mem_ctrl_pwr_2;
486#[doc = "SDMA_MEM_CTRL_0 register accessor: an alias for `Reg<SDMA_MEM_CTRL_0_SPEC>`"]
487pub type SDMA_MEM_CTRL_0 = crate::Reg<sdma_mem_ctrl_0::SDMA_MEM_CTRL_0_SPEC>;
488#[doc = "Control the Deep Sleep function of SRAM Macro for the SDMA power domain"]
489pub mod sdma_mem_ctrl_0;
490#[doc = "SDMA_MEM_CTRL_1 register accessor: an alias for `Reg<SDMA_MEM_CTRL_1_SPEC>`"]
491pub type SDMA_MEM_CTRL_1 = crate::Reg<sdma_mem_ctrl_1::SDMA_MEM_CTRL_1_SPEC>;
492#[doc = "Control the Shut Down function of SRAM Macro for the SDMA power domain"]
493pub mod sdma_mem_ctrl_1;
494#[doc = "MEM_PWR_DWN_CTRL register accessor: an alias for `Reg<MEM_PWR_DWN_CTRL_SPEC>`"]
495pub type MEM_PWR_DWN_CTRL = crate::Reg<mem_pwr_dwn_ctrl::MEM_PWR_DWN_CTRL_SPEC>;
496#[doc = "Memory Power Down Control"]
497pub mod mem_pwr_dwn_ctrl;
498#[doc = "PMU_TIMER_CFG_0 register accessor: an alias for `Reg<PMU_TIMER_CFG_0_SPEC>`"]
499pub type PMU_TIMER_CFG_0 = crate::Reg<pmu_timer_cfg_0::PMU_TIMER_CFG_0_SPEC>;
500#[doc = "Configuration for the PMU timer time-out period"]
501pub mod pmu_timer_cfg_0;
502#[doc = "PMU_TIMER_CFG_1 register accessor: an alias for `Reg<PMU_TIMER_CFG_1_SPEC>`"]
503pub type PMU_TIMER_CFG_1 = crate::Reg<pmu_timer_cfg_1::PMU_TIMER_CFG_1_SPEC>;
504#[doc = "Control wether the PMU timer is enabled or disabled"]
505pub mod pmu_timer_cfg_1;
506#[doc = "PDWU_Timer_CFG register accessor: an alias for `Reg<PDWU_TIMER_CFG_SPEC>`"]
507pub type PDWU_TIMER_CFG = crate::Reg<pdwu_timer_cfg::PDWU_TIMER_CFG_SPEC>;
508#[doc = "Control the delay for power-on after wake-up event. Applies to all power domains"]
509pub mod pdwu_timer_cfg;
510#[doc = "FFE_FB_PF_SW_PD register accessor: an alias for `Reg<FFE_FB_PF_SW_PD_SPEC>`"]
511pub type FFE_FB_PF_SW_PD = crate::Reg<ffe_fb_pf_sw_pd::FFE_FB_PF_SW_PD_SPEC>;
512#[doc = "Registers for triggering power-down events in the FFE, FB and PF power domains."]
513pub mod ffe_fb_pf_sw_pd;
514#[doc = "M4_SRAM_SW_PD register accessor: an alias for `Reg<M4_SRAM_SW_PD_SPEC>`"]
515pub type M4_SRAM_SW_PD = crate::Reg<m4_sram_sw_pd::M4_SRAM_SW_PD_SPEC>;
516#[doc = "Register for triggering power-down events in M4 SRAM power domains. (RWHC)"]
517pub mod m4_sram_sw_pd;
518#[doc = "MISC_SW_PD register accessor: an alias for `Reg<MISC_SW_PD_SPEC>`"]
519pub type MISC_SW_PD = crate::Reg<misc_sw_pd::MISC_SW_PD_SPEC>;
520#[doc = "Register for triggering power down events in MISC power domains + some general purpose SFR's (RWHC)"]
521pub mod misc_sw_pd;
522#[doc = "AUDIO_SW_PD register accessor: an alias for `Reg<AUDIO_SW_PD_SPEC>`"]
523pub type AUDIO_SW_PD = crate::Reg<audio_sw_pd::AUDIO_SW_PD_SPEC>;
524#[doc = "Register for triggering power-down events in Audio power domains. (RWHC)"]
525pub mod audio_sw_pd;
526#[doc = "FFE_FB_PF_SW_WU register accessor: an alias for `Reg<FFE_FB_PF_SW_WU_SPEC>`"]
527pub type FFE_FB_PF_SW_WU = crate::Reg<ffe_fb_pf_sw_wu::FFE_FB_PF_SW_WU_SPEC>;
528#[doc = "Registers for triggering wake-up events in the FFE, FB and PF power domains."]
529pub mod ffe_fb_pf_sw_wu;
530#[doc = "M4_SRAM_SW_WU register accessor: an alias for `Reg<M4_SRAM_SW_WU_SPEC>`"]
531pub type M4_SRAM_SW_WU = crate::Reg<m4_sram_sw_wu::M4_SRAM_SW_WU_SPEC>;
532#[doc = "Register for triggering wake-up events in M4 SRAM power domains. (RWHC)"]
533pub mod m4_sram_sw_wu;
534#[doc = "MISC_SW_WU register accessor: an alias for `Reg<MISC_SW_WU_SPEC>`"]
535pub type MISC_SW_WU = crate::Reg<misc_sw_wu::MISC_SW_WU_SPEC>;
536#[doc = "Register for triggering wake up events in MISC power domains + some general purpose SFR's (RWHC)"]
537pub mod misc_sw_wu;
538#[doc = "AUDIO_SRAM_SW_WU register accessor: an alias for `Reg<AUDIO_SRAM_SW_WU_SPEC>`"]
539pub type AUDIO_SRAM_SW_WU = crate::Reg<audio_sram_sw_wu::AUDIO_SRAM_SW_WU_SPEC>;
540#[doc = "Register for triggering wake-up events in Audio power domains. (RWHC)"]
541pub mod audio_sram_sw_wu;
542#[doc = "PMU_STM_PRIORITY register accessor: an alias for `Reg<PMU_STM_PRIORITY_SPEC>`"]
543pub type PMU_STM_PRIORITY = crate::Reg<pmu_stm_priority::PMU_STM_PRIORITY_SPEC>;
544#[doc = "Power Management Unit Software Test Mode priority control"]
545pub mod pmu_stm_priority;
546#[doc = "M4SRAM_SSW_LPMF register accessor: an alias for `Reg<M4SRAM_SSW_LPMF_SPEC>`"]
547pub type M4SRAM_SSW_LPMF = crate::Reg<m4sram_ssw_lpmf::M4SRAM_SSW_LPMF_SPEC>;
548#[doc = "Control for M4SRAM power domain light sleep mode"]
549pub mod m4sram_ssw_lpmf;
550#[doc = "M4SRAM_SSW_LPMH_MASK_N register accessor: an alias for `Reg<M4SRAM_SSW_LPMH_MASK_N_SPEC>`"]
551pub type M4SRAM_SSW_LPMH_MASK_N =
552 crate::Reg<m4sram_ssw_lpmh_mask_n::M4SRAM_SSW_LPMH_MASK_N_SPEC>;
553#[doc = "Control masking for the LPMH (Low Power Mode header - deep sleep circuit)"]
554pub mod m4sram_ssw_lpmh_mask_n;
555#[doc = "FBVLPMinWidth register accessor: an alias for `Reg<FBVLPMINWIDTH_SPEC>`"]
556pub type FBVLPMINWIDTH = crate::Reg<fbvlpmin_width::FBVLPMINWIDTH_SPEC>;
557#[doc = "Configuration for the amount of IDLE cycles before powering on the FB domain"]
558pub mod fbvlpmin_width;
559#[doc = "APRebootStatus register accessor: an alias for `Reg<APREBOOTSTATUS_SPEC>`"]
560pub type APREBOOTSTATUS = crate::Reg<apreboot_status::APREBOOTSTATUS_SPEC>;
561#[doc = "Indicates if AP nees to reload the code to SRAM"]
562pub mod apreboot_status;
563#[doc = "GEN_PURPOSE_0 register accessor: an alias for `Reg<GEN_PURPOSE_0_SPEC>`"]
564pub type GEN_PURPOSE_0 = crate::Reg<gen_purpose_0::GEN_PURPOSE_0_SPEC>;
565#[doc = "Configure FB config enable and wether Audio SRAM can be put into Deep Sleep by the Audio hardware"]
566pub mod gen_purpose_0;
567#[doc = "FB_ISOLATION register accessor: an alias for `Reg<FB_ISOLATION_SPEC>`"]
568pub type FB_ISOLATION = crate::Reg<fb_isolation::FB_ISOLATION_SPEC>;
569#[doc = "Control the FB Isolation"]
570pub mod fb_isolation;
571#[doc = "GEN_PURPOSE_1 register accessor: an alias for `Reg<GEN_PURPOSE_1_SPEC>`"]
572pub type GEN_PURPOSE_1 = crate::Reg<gen_purpose_1::GEN_PURPOSE_1_SPEC>;
573#[doc = "Control for: Wether ext-interrupt can be used to wake up FFE, and clock switching for FFE/M4 power domains"]
574pub mod gen_purpose_1;